P2 counters question

Bill Henning

I know the docs are not finished...

Is it possible to do the following with the new counters:

- set initial output state (0 or 1)
- toggle the pin every N clocks (where N = 1...x in clkfreq's)
- limit the toggling to a specified COUNT

ie

generate 8 pulses at 100MHz (assuming 200MHz cpu clock) on pin X

generate 32 pulses at 100Mhz (assuming 200Mhz cpu clock) on pin X

...

generate 256 pulses at 100Mhz

do the above, but with differential pin pair output

--- If not possible ---

Are the counter instructions deterministic enough that we can start a count with the initial state we want, perform two instructions per count, and stop the counter... and we would be guaranteed not get any extra pulses?

cgracey

Bill Henning wrote: »

I know the docs are not finished...

Is it possible to do the following with the new counters:

- set initial output state (0 or 1)
- toggle the pin every N clocks (where N = 1...x in clkfreq's)
- limit the toggling to a specified COUNT

ie

generate 8 pulses at 100MHz (assuming 200MHz cpu clock) on pin X

generate 32 pulses at 100Mhz (assuming 200Mhz cpu clock) on pin X

...

generate 256 pulses at 100Mhz

do the above, but with differential pin pair output

--- If not possible ---

Are the counter instructions deterministic enough that we can start a count with the initial state we want, perform two instructions per count, and stop the counter... and we would be guaranteed not get any extra pulses?

That's a neat idea - and it would take way less than what makes up a CTR to realize.

Bill Henning

Thanks!

I would REALLY appreciate it if this made it in.

It would make various clocked bit-banged protocols much easier and faster.

It would make fast nibble-banged QSPI easy

And it would make a good generic clocking mechanism for the internal SERDES clock (another use for it)

cgracey wrote: »

That's a neat idea - and it would take way less than what makes up a CTR to realize.

Bill Henning

And if N=0, output the system clock (or its inverse, based on stated start value)

Also, COUNT would be the number of times to toggle; so an odd count would leave the output in the opposite state it started from

Initial=0,N=1,COUNT=15

(logic level output)

01010101010101010101

toggled 15 times, output starts at 0, ends in a 1

Initial=0,N=1,COUNT=16

(logic level output)

010101010101010101010

I came up with this while thinking of how to do fast SPI and QSPI before SERDES and potential 4 bit XFER

By providing the initial pin state, we can generate rising edge triggered and falling edge triggered clocks

Same counter mode would also work well as the P2 generated SPI master clock for SERDES

Could also be used for slow XFER's (for LCD's, QSPI, etc)

Heck, it could be an instruction...

CLOCKFRQ #/divider ' 0=clkfreq, 1..511=divider

followed by

CLOCKGEN pin, #/count, #0|1 initial state ' maybe count=0 means infinite count, initiates background clock pulses

Tubular

Another way to do it might be to have a 'stop if PHSx is exactly zero' mode, set when configuring the CTR initially.

It would then be up to the user to seed the FRQx and PHSx registers to get the desired number of pulses at any frequency they like.

Could be useful for sine bursts too, though I think Chip included a rollover instruction to aid this

Cluso99

I am sure the counters could be put to better use with a few variations, like used to clock the SERDES in or out, as well as outputting this clock. Inversion permits I2C and other protocols where the clock edge is in the middle of the bit.

Hopefully this is on the table together with SERDES. I think the SERDES has way more uses than just serial.

jmg

Bill Henning wrote: »

Is it possible to do the following with the new counters:

- set initial output state (0 or 1)
- toggle the pin every N clocks (where N = 1...x in clkfreq's)
- limit the toggling to a specified COUNT

That would probably need an extra control register per timer (maybe an extra one is there already for True PWM modes ?)

If not, an alternative would be to have one timer gated by the MSB of other, which would be clocked by the First timer Overflow.
One timer would set the Count and one would set the /N ?

jmg

I'll add a timer feature detail request, since this is a Timers thread.


For a pair of Counter/Timers :

* Ability to have Atomic control of capture of both Timer values, from pin Edge.
plus
* Ability to Clock from SysCLK, or a Pin Edge

In use you then have a simple loop of either

Loop1
   Wait Some Gate Time
   Disable both captures on same clock (atomic)
   Read capture Registers.
   Enable both captures on same clock (atomic)
   GOTO Loop1

or

Loop2
   Wait Some Gate Time
   Enable both captures on same clock (atomic)
   PollForCapture 
   Disable both captures on same clock(atomic)
   Read capture Registers.
   GOTO Loop2

Loop1 rounds-down, and Loop2 is round-up, to nearest whole cycle dN and dT values.
From there, a reciprocal counter is simple SW.
This Atomic topology loses no edge information, and can run multiple precision counters.
With no lost edges, a background total can sum dN and dT for higher precision, longer update results.

Logic cost of this should be very small, it may just need some flag-aliases.

jmg

Bill Henning wrote: »

Is it possible to do the following with the new counters:

- set initial output state (0 or 1)
- toggle the pin every N clocks (where N = 1...x in clkfreq's)
- limit the toggling to a specified COUNT

Just reading another thread, and it occurs that this feature would allow simple SW (even the Monitor?) to generate a wide range of accurate pulses.
The SW + Serial link says when to start, and the pulse is managed in HW, after the regs are set.
If the Monitor can R/W any register (Which I guess is standard) then this becomes easy.