Everything is pipelined, so it should be fairly easy to modify. You will lose the possibility to use the next modified instruction (not available in P1 for another 4 clocks), and there will be some latency for opcodes after djnz, tjz and tjnz... but they are in the P1 anyways.
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Sounds great.
Another suggestion is to make the opcode values as defines, so you can choose P1 Binary, or P2 Binary versions.
This would allow a 2 Clock Shrink-P2 Cog, to be looked at, than can be driven from a P2 ASM (subset).
Call this P2S for (Shrink/Subset)
The idea is to clone the P1 core operation, and then add a sprinkle of P2 opcodes, but keeping the LOGIC area under the RAM area. (present P1 Logic is much less than P1 COG RAM area, Present P2 Logic is much larger than P2 COG RAM )
David, look on the 5W thread from the date/time of my post above, backwards.
Thanks! I see it now. It doesn't look like he's offering to make it available though. I'd still be interested in a port of Ale's P1 COG to the DE0-Nano.
It seems I posted the results of my ALU test ... I should use more descriptive names for files.
I updated the repository with a better and HUB-aware version. At least it sort of works for the bemicro. There is a serial console output with processor debug info.
The serial output should show cog address, opcode and HUB address and data. At least it works in the simulator.
Is someone there ?... it seems that all the excitement goes to the new P1+... That chip will be a blast !
Ale, I look here perhaps once a week. But yes, I think currently the action is on the P1+/P2.
A couple of years ago and this would have been a killer thread! Once the other dust settles I am sure the interest will pick up here.
It should be possible to test new instructions and features out here. Or just adding a fewmore i/o.
So please don't lose heart due to the lack of enthusiasm.
I'm out here. I've just never built anything for an FPGA before and haven't used the Altera tools (Quartus) for anything other than loading Chip's P2 emulation images. I'm facing a bit of a learning curve before I can get to doing anything useful with my BE Micro....I'll get there slowly but surely.
Comments
Sounds great.
Another suggestion is to make the opcode values as defines, so you can choose P1 Binary, or P2 Binary versions.
This would allow a 2 Clock Shrink-P2 Cog, to be looked at, than can be driven from a P2 ASM (subset).
Call this P2S for (Shrink/Subset)
The idea is to clone the P1 core operation, and then add a sprinkle of P2 opcodes, but keeping the LOGIC area under the RAM area. (present P1 Logic is much less than P1 COG RAM area, Present P2 Logic is much larger than P2 COG RAM )
I updated the repository with a better and HUB-aware version. At least it sort of works for the bemicro. There is a serial console output with processor debug info.
The serial output should show cog address, opcode and HUB address and data. At least it works in the simulator.
Is someone there ?... it seems that all the excitement goes to the new P1+... That chip will be a blast !
A couple of years ago and this would have been a killer thread! Once the other dust settles I am sure the interest will pick up here.
It should be possible to test new instructions and features out here. Or just adding a fewmore i/o.
So please don't lose heart due to the lack of enthusiasm.
For sure we are out here. And totally fascinated. Please continue. No time to play unfortunately.
How about posting you project at opencores.org ?
I'm out here. I've just never built anything for an FPGA before and haven't used the Altera tools (Quartus) for anything other than loading Chip's P2 emulation images. I'm facing a bit of a learning curve before I can get to doing anything useful with my BE Micro....I'll get there slowly but surely.
What I've looked at is impressive and exciting!