SOLVED: Setting up SERIN/OUT (Serial Transceivers)
mindrobots
Posts: 6,506
I'm trying to use the serial transceivers and having trouble making them work. I'm assuming I'm doing something wrong in the setup portion.
I'm trying to replace the bit-banged I/O in pfth with the new SERIN/OUT so once I get a character in, I should be in solid code.
Am I missing something in my setup? The long that is generated appears to have the correct bits set for enabling the RX/TX (8 bit non-inverting) and the proper pin numbers. If I understand the bit period parameter, I think mine should work.
Any thoughts? Need to wrap my knuckles for something stupid?
Thanks!!
con _clkmode = xtal1+pll16x _clkfreq = 80_000_000 rx_pin = 91 tx_pin = 90 DAT org 0 enter jmp #init sera long <<16 + rx_pin<<9 + <<7 + tx_pin ' percent 10 is before the <<16 and the <<7 but the forum ate them bit_period long _clkfreq / 115_200 init setsera sera,bit_period ' setup ser . . . serina x . . . serouta x
I'm trying to replace the bit-banged I/O in pfth with the new SERIN/OUT so once I get a character in, I should be in solid code.
Am I missing something in my setup? The long that is generated appears to have the correct bits set for enabling the RX/TX (8 bit non-inverting) and the proper pin numbers. If I understand the bit period parameter, I think mine should work.
Any thoughts? Need to wrap my knuckles for something stupid?
Thanks!!
Comments
Try inserting the following CLKSET instruction
Edit: Make sure you enable the tx_pin direction with a clrp #tx_pin as well.
I'd been looking at Chip's monitor code. That code looked a lot more complicated than the examples in the manual. I was trying to follow those. The monitor also has the ctra setup in there for the baud detect.
I'll try the proper clk setup even though those lines are from p2 pfth and appear to work.
Thanks!
BTW Don't forget the DE0 only has CTRA now.
I have a few changes to make!
Thanks!
I added that to my code from the first post after the setsera and it started working!
Amazing! Serial I/O with 4 instructions!!
2 to set it up and 1 each for input and output. Pretty dang slick!!
Thanks Chip!!
Now it's time to move the stacks into AUXRAM.
EDIT: 460,800 baud is pretty darn quick! I'd go faster but it's bedtime!
I've been running my puTTY connection at 2Mbits since last night. That's stupid fast for terminal I/O but fun to see. I stopped at 2Mbits since I was starting to have trouble. I may have hit either a puTTY limit or a Win7 serial I/O limit (or I guess an FTDI limit) at that point.
Now, it makes me want to have a second P2 core so the two can chatter back and forth. (by forth, I mean as in to and fro, not Forth....don't want to start any battles!! )
IIRC I read somewhere on this forum of FTDI chips having problems over 1.5M baud.
Yes, data gets lost. I've found that 1M baud is safe, so I use that.
It depends on the device.
The FT232H/2232H etc are better behaved at high Baud ( > 1M) speeds.
Std speed parts start to add more stop bits in what they send, as the baud rates climb, so the data flow is lower than you might expect.
Loopback tests seem to be ok, but of course, they are no longer true packed-data tests.
The toughest test would be high baud rates, 1 stop bit, no extra gaps, aka continual data.
Adding extra stop bits, would probably make it more reliable.
Not sure if SerDes can do that in HW ?
There is also a Fast Serial (sync) mode the FTDI HS parts support, that accepts a FSSCK to 50MBd
It is a half-duplex state machine, and has a simple HW handshake, and 9 data bits.
50MBd would be nice to have