How to divide a clock input?

T Chap

entry   'mov     ctra, ctra_            'REQD establish mode and start counter
        movs    ctra,#27     'apin   ' count external clock p27
        movd    ctra,#16      'bpin   'carry out on B
        movs    ctrb,#16      'count p16
        movi    ctra,#%01011_000    'init ctra pos edge det  with carry  to Bpin p16
        movi    ctrb,#%01010_000    'init ctra count only pin p16
        mov     frqa, freq      '$8000_0000   same as dividing clock at p27 by 2
        mov     frqb, #1
        or      dira, LEDMASK
        or      dira, bclkMSK
        mov     phsa, phsrst
        andn    outa, ledmask
        andn    outa, bclkMSK

:loop   mov     new, phsb            'set counter to 0
        cmp     new, count1 wz, wc   'REQD change val for LED blinking debug
if_ae   or      outa, bclkMSK        'ON
if_ae   mov     temp,  cnt
if_ae   add     temp,  Waitlen
if_ae   waitcnt temp, temp

if_ae   andn    outa, bclkMSK        'OFF
if_ae   mov     phsa, phsrst
if_ae   mov     phsb, phsrst

        jmp     #:loop          'REQD

This isn't working but I was hoping someone had a better idea to accomplish this.

_clkmode = xtal1 + pll8x
_xinfreq = 12_288_000

A clock is into p27 at a rate of 384 x 44100 = 16,934,400.

I want to derive another clock from that input that is 384/48 = 8 cycles long, so 4 clocks is high and 4 clocks is low. I have tried setting a counter in posedge mode that counts up 4 clocks, then compare phsa with a value of 4. This is close but I cannot get it as close as I'd like. So the goal instead of counting up to 4 is to let the counter flip a pin every 4 clocks, and then just do something when the pin goes high. The example above is the idea but doesn't work. Any other ideas to accomplish this?

One part of the problem seems to be that in PASM I can't reset phsa, it just keeps counting. The spin equivalent does allow resetting phsa and starting over. The manual states it is a read write register, but also alludes to not being able to write to it.

jmg

The P1 counter has no mode to both externally clock, and create a Counter output.
( Hopefully P2 counters will allow both, as well as HW edge capture.)

ctra,#%01011_000 ' says POSEDGE detector w/ feedback Pin : !A1
ie that is just a delayed copy of the Fi.

On the modes where Counter output is possible :
%00100
%00101
%00110
%00111

there is no GATE or external Fi support.

T Chap

entry   'mov     ctra, ctra_            'REQD establish mode and start counter

        movi    ctra,#%01010
        movs    ctra,#apin  'apin    count external clock p27
        mov     frqa, freq     '$4000_0000   same as dividing clock at p27 by 2
        or      dira, LEDMASK
        or      dira, bclkMSK

        mov     new, phsa
        'or      outa, ledmask   'test the LED
:test1  mov     temp, phsa   ' check bit32 in phsa for a 1
        and     temp, phsamask  wz, wc   'and bit32 to phsa to check for true
if_c    mov     outa, ledmask

:loop
        'mov     phsa, #0
        jmp     #:test1

Another idea(not working yet in this mode) that watches phsa and AND's the carry bit to phsamask (phsamask LONG | <32), check for c flag and turn on an LED which the LED represents the new clock.

Edit: This is looking like a possibility:

:test1  mov     temp, phsa   ' check bit32 in phsa for a 1
        and     temp, phsamask  wz, wc   'and bit32 to phsa to check for true
if_c    mov     outa, ledmask

:loop
if_c    mov     phsa, #0
if_c    andn    outa, ledmask
         jmp     #:test1
         mov     new, phsb  [/code

freq   long   $4000_0000

T Chap

entry   'mov     ctra, ctra_            'REQD establish mode and start counter

        movi    ctra,#%01010
        movs    ctra,#apin  'apin    count external clock p27
        'movd    ctra,#bpin  'bpin    carry out on B
        'movs    ctrb,#16      'count p16
        'movi    ctra,#%01011_000    'init ctra pos edge det  with carry  to Bpin p16
        'movi    ctrb,#%01010_000    'init ctra count only pin p16
        mov     frqa, freq     '$4000_0000   same as dividing clock at p27 by 2
        'mov     frqb, #1
        or      dira, LEDMASK
        or      dira, bclkMSK
        or      LEDMASK, bclkMSK   'merge for debug using LED and bitclock p15
        mov     new, phsa
        'or      outa, ledmask
:test1  mov     temp, phsa   ' check bit32 in phsa for a 1
        and     temp, phsamask  wz, wc   'and bit32 to phsa to check for true
if_c    mov     outa, ledmask
        nop
        nop
        nop
        nop
:loop
if_c    mov     phsa, #0
if_c    andn    outa, ledmask
        nop
        nop
        jmp     #:test1

I want a high cycle of .2363 and period of .4724. You can get either larger or smaller times, but the increments are just too big to nail it. This will get by.

jmg

Another approach would be to skip the Prop, and use a 74HC6323 (SO8), or a HC4020 as the /8, at least while testing ?

Mark_T

The 4020 can divide by 2 or 16, 32, 64 or higher, but not by 4 or 8!

74HC6323 Can't find that at my supplier, though digikey stock it, the common ripple counter is the
74HC393 (2 4-bit counters which can be chained) and its dirt cheap and may be more widely available.

jmg

Mark_T wrote: »

The 4020 can divide by 2 or 16, 32, 64 or higher, but not by 4 or 8!

Oops, I meant the 4040.

Mark_T wrote: »

74HC6323 Can't find that at my supplier, though digikey stock it,

It's a nice part that includes the Xtal OSC buffer, and comes in a smaller SO8, but seems to have never hit critical mass.
It is very easy to apply, and small, even if a bit expensive for what it is*

There is a surprising lack of a simple/cheap logic device that has Xtal Osc and simple dividers.
Torex do some, but they are laser-programmed so are semi custom.

* For a more complex part, but a better price/performance point, look at the SI5351A-B-GT
This is $1.30/1+, and can generate pretty much ANY frequency you want 10KHz~160MHz, just add a std 25/27MHz Xtal

I also like the Si504, easier to configure than SI5351A-B-GT, and includes the OSC element for $3.07/1+ @ Digikey,