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New Altera FPGA board - perfect for 2-3 cog P2 emulation! $199 — Parallax Forums

New Altera FPGA board - perfect for 2-3 cog P2 emulation! $199

Bill HenningBill Henning Posts: 6,445
edited 2014-01-24 15:50 in Propeller 2
Altera DE1-SoC Board

Guys - it seems to me that this would support 3 cogs, 256KB hub, and not need an extension board!

At $200, it would allow a LOT more people to get involved with P2 testing and maybe even P3 development.

FPGA Device

Cyclone V SoC 5CSEMA5F31C6 Device
Dual-core ARM Cortex-A9 (HPS)
85K Programmable Logic Elements 2-3 cogs!
4,450 Kbits embedded memory 256KB hub!
6 Fractional PLLs
2 Hard Memory Controllers easy SDRAM for Chip

Configuration and Debug

Quad Serial Configuration device – EPCQ256 on FPGA
On-Board USB Blaster II (Normal type B USB connector)

Memory Device

64MB (32Mx16) SDRAM on FPGA - same as on the Prop2 module!
1GB (2x256Mx16) DDR3 SDRAM on HPS
Micro SD Card Socket on HPS

Communication

Two Port USB 2.0 Host (ULPI interface with USB type A connector)
USB to UART (micro USB type B connector)
10/100/1000 Ethernet
PS/2 mouse/keyboard
IR Emitter/Receiver


[B]Connectors[/B]

Two 40-pin Expansion Headers
One 10-pin ADC Input Header
One LTC connector (One Serial Peripheral Interface (SPI) Master ,one I2C and one GPIO interface )


Display

24-bit VGA DAC - could be mapped to P2 DACs in Verilog!

Audio

24-bit CODEC, Line-in, line-out, and microphone-in jacks

Video Input

TV Decoder (NTSC/PAL/SECAM) and TV-in connector

Switches, Buttons and Indicators

4 User Keys (FPGA x4)
10 User switches (FPGA x10)
11 User LEDs (FPGA x10 ; HPS x 1)
2 HPS Reset Buttons (HPS_RST_n and HPS_WARM_RST_n)
Six 7-segment displays

Sensors

G-Sensor on HPS

Power

12V DC input


See http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=167&No=836&PartNo=2

Comments

  • rjo__rjo__ Posts: 2,114
    edited 2014-01-24 08:13
    Bill,

    I like the video-in and the memory… but I also like the convenience of the video-out and separate DACs on the adapter board.
    I only have a Nano, so if the Chip's massive changes don't fit, I'm high and dry… not for long, since Ken has our backs on this.

    Rich
  • Bill HenningBill Henning Posts: 6,445
    edited 2014-01-24 08:19
    I am *REALLY* looking forward to the FPGA board Parallax is cooking up; but I fear it is going to be in the $300-$500 range, which would limit the number of forumistas that can play with it.

    Those of us with DE2-115's will still be fine... but I am just itching to try fast p2-p2 comms.

    What I liked about this $200 board was the two 40 pin connectors; that would expose 72 I/O's, so with the SDRAM & VGA & PS/2 we could have access to the rest of the P2 pins, for hardware hacking :)
    rjo__ wrote: »
    Bill,

    I like the video-in and the memory… but I also like the convenience of the video-out and separate DACs on the adapter board.
    I only have a Nano, so if the Chip's massive changes don't fit, I'm high and dry… not for long, since Ken has our backs on this.

    Rich
  • TorTor Posts: 2,010
    edited 2014-01-24 08:23
    A nice board. But for a hobbyist the price is still out of range IMO. For me it would anyway be closer to $340, if not more - shipping has probably increased since I last checked Terasic. VAT and charges on top of shipping, so all in all it gets rather expensive. But the board does look nice.

    -Tor
  • Bill HenningBill Henning Posts: 6,445
    edited 2014-01-24 08:29
    YUCK - almost doubles the price!

    I am thinking of getting one of these boards regardless of P2 support; having all that I/O easily available is very tempting.
  • rjo__rjo__ Posts: 2,114
    edited 2014-01-24 08:30
    Chip is good at multitasking:) If we drop the Nano… then it would be reasonable to assume that he will fill the vacuum with something.
    I really didn't care about the price of the new Parallax-FPGA boards (as long as they generated profits:). But now that you mention it… P2<->P2 experiments could get expensive and technically
    challenging. Maybe Ken could offer a combo pack with a little engineering thrown in…hmmm, wonder who could do the work?
  • Bill HenningBill Henning Posts: 6,445
    edited 2014-01-24 08:42
    Yep.

    I hope Chip can chop enough (CTRB? CORDIC?) to keep the Nano viable for at least comm/io testing; I have three of them in the lab - that plus my DE2-115 would make a nice little network for testing P2 comms :)
    rjo__ wrote: »
    Chip is good at multitasking:) If we drop the Nano… then it would be reasonable to assume that he will fill the vacuum with something.
    I really didn't care about the price of the new Parallax-FPGA boards (as long as they generated profits:). But now that you mention it… P2<->P2 experiments could get expensive and technically
    challenging. Maybe Ken could offer a combo pack with a little engineering thrown in…hmmm, wonder who could do the work?
  • pik33pik33 Posts: 2,388
    edited 2014-01-24 10:35
    A good board. Academic price is $150. We have Terasic's reseller in Poland so maybe it will be not $340 equivalent.

    A cheap board with a lot of power. Maybe it will be possible to build self-programming P2 environment with it, there is a Linux for this board available on Terasic's site.
  • User NameUser Name Posts: 1,451
    edited 2014-01-24 10:42
    pik33 wrote: »
    Maybe it will be possible to build self-programming P2 environment with it, there is a Linux for this board available on Terasic's site.

    Wouldn't that be cool!!

    I wonder how big the Linux footprint would be?
  • Bill HenningBill Henning Posts: 6,445
    edited 2014-01-24 11:01
    I just had an interesting thought...

    I wonder if Altera would do a short run of these boards with the 149K LE version of the SoC? I think it is available in a compatible package to the 85K LE used on the board.

    That might save Parallax a lot of development money and time, and I suspect Altera could sell the resulting board for ~$300 if it wanted to.

    149K LE's would likely get us six cogs (ok, maybe only 5) but no need for an expansion board due to built-in VGA DAC's!
  • jmgjmg Posts: 15,175
    edited 2014-01-24 11:11
    Impressive Board, and another option - SDRAM and VGA are especially appealing.
    Parallax could get one of these, as they flesh out their own designs.

    I'm sure effort will go into a Nano Build, it may be size-optimized, or some rare-resource may be trimmed (Cordic?), or there may even be two builds (choose one..), and there is also the existing BEmicro board, with 12% more LEs as a sub $50 Single COG point
  • Bill HenningBill Henning Posts: 6,445
    edited 2014-01-24 11:15
    There are fairly cheap cables that break out VGA to component video...

    I really must check out that BE Micro board...
    jmg wrote: »
    Impressive Board, and another option - SDRAM and VGA are especially appealing.
    Parallax could get one of these, as they flesh out their own designs.

    I'm sure effort will go into a Nano Build, it may be size-optimized, or some rare-resource may be trimmed (Cordic?), or there may even be two builds (choose one..), and there is also the existing BEmicro board, with 12% more LEs as a sub $50 Single COG point
  • LeonLeon Posts: 7,620
    edited 2014-01-24 11:53
    There are fairly cheap cables that break out VGA to component video...

    I really must check out that BE Micro board...

    Verical (part of Arrow) has 901 available:

    https://www.verical.com/#searchCriterion=1&landingPage=catalogMpnView&searchName=&_i_=1&searchTerm=BEMICRO%20CV

    I bought mine from them.
  • Bill HenningBill Henning Posts: 6,445
    edited 2014-01-24 11:56
    Thanks Leon, I think I'll pick up a couple. Seems like a nice little board, I was just reading its manual.
    Leon wrote: »
  • LeonLeon Posts: 7,620
    edited 2014-01-24 12:01
    Here is a very simple VHDL test program for it:
    -- Simple test program for BeMicro CV kit
    --
    -- Lights USER_LED0 when Tact1 button is pressed
    --
    -- USER_LED0 - Pin U1
    -- Tact1 - Pin H18
    
    LIBRARY IEEE;
    USE IEEE.STD_LOGIC_1164.all;
    
    
    ENTITY Test IS
    	PORT
    	(
    		USER_LED0	: OUT	STD_LOGIC;
    		Tact1			: IN STD_LOGIC
    	);
    END Test;
    
    
    ARCHITECTURE a OF Test IS
                 
       attribute chip_pin : string;
       attribute chip_pin of USER_LED0 : signal is "U1";
       attribute chip_pin of Tact1 : signal is "H18";
    
    
    BEGIN
    	USER_LED0 <= Tact1;
    END a;
    

    I don't like Verilog.
  • jmgjmg Posts: 15,175
    edited 2014-01-24 15:27
    Thanks Leon, I think I'll pick up a couple. Seems like a nice little board, I was just reading its manual.

    Might pay to pause, until Chip confirms he can build for that target OK ?
    Certainly looks good on paper.
  • TubularTubular Posts: 4,705
    edited 2014-01-24 15:50
    The other thing is Terasic announce their designs fairly early and it takes several months before free stock is available.

    The $300 SoC version (P0160) is now available from Mouser (35 in stock) but has gone out of stock again at Terasic.
    The $179 GX version (P0150) doesn't seem to be anywhere but due in Feb at Terasic.

    These are boards we were discussing last September so we need to allow a few months, or get some kind of supply guarantee. I would hope Parallax have other options within 6 months (silicon, and/or their own 5C A7 version). But yes, looks like a really nice board for the price, thanks Bill
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