Ramdom qusetion about my wifes table
TC
Posts: 1,019
Hello all,
As most of you know, I am building a 16x32 RGB coffee table for my wife.If not here is the thread.
Last night I came up with a thought. Could the matrix be refreshed from logic gates? instead of the prop constantly refreshing the matrix.
Just wondering (I don't think I will make it happen), could this work?
I am going to use Texas Instruments TLC5940 for the columns. A 192-bit (per chip) is shifted in, then latched.
I was thinking, why not use some kind of parallel RAM, load it in to a parallel to serial converter, shift it out, do it again for the rest of the chips. and controlling this all is a simple counter. The counter is controlling the RAM keeping track of when to latch the rows, etc...
And there would be 2 arrays in RAM, one for what the matrix is using, and one for the prop to load. once the prop has finished loading the RAM, it would take something LOW (or HIGH) so the matrix would now use that RAM location on the next start of refreshing the matrix.
I might build this, just for fun maybe a 8x16 matrix.
Again, this is just an idea. What do you guys think?
Thanks
TC
As most of you know, I am building a 16x32 RGB coffee table for my wife.If not here is the thread.
Last night I came up with a thought. Could the matrix be refreshed from logic gates? instead of the prop constantly refreshing the matrix.
Just wondering (I don't think I will make it happen), could this work?
I am going to use Texas Instruments TLC5940 for the columns. A 192-bit (per chip) is shifted in, then latched.
I was thinking, why not use some kind of parallel RAM, load it in to a parallel to serial converter, shift it out, do it again for the rest of the chips. and controlling this all is a simple counter. The counter is controlling the RAM keeping track of when to latch the rows, etc...
And there would be 2 arrays in RAM, one for what the matrix is using, and one for the prop to load. once the prop has finished loading the RAM, it would take something LOW (or HIGH) so the matrix would now use that RAM location on the next start of refreshing the matrix.
I might build this, just for fun maybe a 8x16 matrix.
Again, this is just an idea. What do you guys think?
Thanks
TC
Comments
http://www.idt.com/products/memory-logic/multi-port-memories/asynchronous-dual-port-rams/5962-88610-2k-x-16-dual-port-ram
2K 16bit wide...
Anyway, I would suggest using parallell/Wide output, not Serial, and just Connect the outputs to a buffer capable of handling the currents needed.
Then use a some sort of decoders (Maybe a couple of 74hc138) to Select rows on the LEDs, while at the same time connecting the 'non-decoded' address lines to the lower address inputs on the RAM.
What you describe is pretty much how video displays were build back in the day, think those old green screen text terminals.
Actually I'm kind of seeing your wife's coffee table as a CPU. It has sixteen 32 bit registers....in 3 banks...it displays it's execution state as it runs...
That RAM would be perfect.
Please excuse my lack of knowledge of logic gates, but could it be possible to do a PWM for each output? Maybe offer 8-bits per color, per pixel?
I was thinking that is how it could of been done before microprocessors.
CPU??? are you refereeing to a microprocessor (the Prop)?
You know that someone may actually build one if you write stuff like that...
No, that would be cheating
Continuing on your theme of using logic to drive the LED display I was meaning you build a CPU out of TTL. Use of discreet transistors or relays earns you extra street cred.
Now the registers, of your CPU (accumulator, program counter, stack pointer, whatever you have) are wired to your coffee table LEDS so that you can see the processors state as it executes.
There we have it, a coffee table that computes!
OK, the "awesome" factor just went up.
I see WTPL coming. It will be a huge hit! (that's Wife Table Programming Language).
Next is WMD (Wife Machine Interface), which could be a row of 16 on/off switches along the table edge (hmm- reminds me of something...), which would enable programming the table computation.
Before long everyone wants to be tablecoding.
Erlend
For example it is possible to write any program give nothing but a "subtract and jump if less" than instruction. "subleq".
So the subleq instruction has three operands or fields;
A, B, C
Which means "subtract contents of address A from content of address B and put the result in address B. Then jump to address C if the result was negative"
That amount of logic should not be so hard to build in TTL.
There are other instructions that could be used for a SIC but the advantage of a "subleq" machine is that there is a high level language, looks like C, compiler available for it by Oleg Mazonka.
References:
http://en.wikipedia.org/wiki/One_instruction_set_computer#Transport_triggered_architecture
http://mazonka.com/subleq/hsq.html
http://mazonka.com/st/lcss.pdf
User present requirements...engineer changes requirements....user receives final product which does not meet requirements....user cancel certain terms of contract...engineer sleeps on couch.
I'm just guessing based on theoretical scenarios.....I've personally never been in this situation...over a SIC coffee table, at least.
That looks very interesting. That requires a more in depth read than I can do at work.
However I feel strange urge to start writing a SIC emulator for the Propeller....must resist...
Very true. But the idea will always be there.
If you start writing it in Forth, you'll stop working on it soon after you start and then have a lot more free time for other projects!
If I start work in Forth it will not just the emulation that is SIC