External RAM adition -- Question to Chip
Sapieha
Posts: 2,964
Hi Chip.
Itis possible that You parallel with SDRAM handler can add handler for SRAMS on same pins.
Example in code section.
Itis possible that You parallel with SDRAM handler can add handler for SRAMS on same pins.
Example in code section.
module SRAM_interface(
in_address,
wr_or_rd,
in_data,
//////////// interface cua SRAM ///////////////////
oSRAM_DQ,
oSRAM_ADDR,
oSRAM_UB_N,
oSRAM_LB_N,
oSRAM_WE_N,
oSRAM_CE_N,
oSRAM_OE_N,
/////////// data for ram COG //////////////////////
data_ram_COG
);
input [17:0]in_address;
input wr_or_rd;
input [15:0]in_data;
inout [15:0] oSRAM_DQ; // SRAM Data bus 16 Bits
output [17:0] oSRAM_ADDR; // SRAM Address bus 18 Bits
output oSRAM_UB_N; // SRAM High-byte Data Mask
output oSRAM_LB_N; // SRAM Low-byte Data Mask
output oSRAM_WE_N; // SRAM Write Enable
output oSRAM_CE_N; // SRAM Chip Enable
output oSRAM_OE_N; // SRAM Output Enable
output [15:0]data_ram_COG;
assign oSRAM_UB_N = 0; // hi byte select enabled
assign oSRAM_LB_N = 0; // lo byte select enabled
assign oSRAM_CE_N = 0; // chip is enabled
assign oSRAM_OE_N = ~oSRAM_WE_N; //output enable is overidden by WE
assign oSRAM_WE_N = ~wr_or_rd;
assign oSRAM_DQ = (~wr_or_rd? 16'hzzzz : in_data );
assign data_ram_COG = oSRAM_DQ;
assign oSRAM_ADDR = in_address;
endmodule
Comments
Many times it will be enough.
But I think You are mising some x512kB
Nice chip but a little slow at 55 - 70nS
It was only to show Chip that it is bigger SRAM's that 512kB
And how much address lines ( and other signals) we need on that addition
Same here, but I may like to burn some more pins and use 32 bits to get an XMMC type of VM running relatively fast from it (up to ~50MIPs) and use the hub RAM almost entirely as a video buffer. Or alternatively, try to run from hub RAM using hub exec and just use the SRAM as a hires + high color depth video buffer that gets low write latency as well providing good read bandwidth for the applications running. I'm also hoping that this video/hub exec combination may work out well with some multitasking. Who exactly controls the SRAM's I/O pins will no doubt become "interesting" to say the least.
Using SDRAM would be nice and cheap but it may not cut it for performance in this type of application. I'm still hoping to figure out how to do it though. Time will tell.