OT: Maskless chip fabs.

Lawson

Watching the Prop2's growing pains has got me wondering why (almost?) none of the old micro-chip process nodes have moved to a maskless process. Particularly the Seiki 4K tv sitting in front of me gets me wondering. It has 3840x2160x3 (a total of 24,883,200 sub-pixels) optical switches updated at 30Hz over HDMI or 120Hz internally. (it's "only" $500) Should be able to easily fit a 1um process mask for 2mm^2 of chip with resolution to spare for anti-aliased edges. (or align multiple exposures for bigger chips) Drop the whole custom layout inside a standard (but versitile) power buss and IO pin frame. Put it in a standard package. (say, a QFP with a power pad) And sell 'em in small lots with a 3-4 week turn around. Not going to fit something complex in that, but I expect it'd be plenty of area for custom analog functions, or a bit of LVDS/PECL/CML glue logic. Heck, add a transparent package option for the opto-electronics guys.

Alternatively, add a "slow lane" to a current fab using e-beam steppers. It'd do maybe 3 wafers a day, but that'd be plenty for prototyping.

Marty

Ken Gracey

Hey Marty. I had to read your thread twice and think about it for a while. I'll only answer from a boring business standpoint.

I can't answer the question about being able to drop a design into a standard frame. I think there would have to be a market for a frame, but that market depends on the customers who might be able to use it.

But if the question pertains mostly to doing quick-turn, non-mask fab runs I know a little bit.

I'm pretty sure that the answer lies in development time and market potential along with return on investment. There's a pretty stiff non-recurring engineering cost with chip design. And putting the design cost aside, there's so much cost related to testing, fabrication, packaging, documentation, software (maybe not, too), layout (maybe) and synthesis software, and developing customer belief behind the product. Let's just plop all these costs into a category called "chip development expense". Recovering the chip development costs is a function of volume, time, unit cost, gross profit.

Engineers are inspired by their beliefs, their reasoning, enthusiasm - all responses to the question "why do this?. But engineers and the ecosystem around them must be fueled for these things to happen. You already know this, I'm sure, as many productive engineers are employed or entrepreneurial.

To recover the design cost requires volume. The non-mask process (I don't know what our foundry calls it exactly - reticle layers?) has a high unit cost per device.

In short, I guess I'd have to say that the chip development expense is really high - especially relative to even a mask set of layers, and that the non-mask process has a higher unit cost which could make it difficult to recover the expenses. Unless the chip is designed for an exact purpose that it'll do really well - maybe at a high price, it could actually make more sense to try to stuff it into an FPGA and sell that device and forgo fabrication.

I think the benefit of the non-mask process is that small companies can turn-and-burn a bit more easily with a lower setup cost. But again, these costs are nothing in comparison to the total chip development costs.

Ken Gracey