OT: Learning Verilog

Seairth

Preparing for the day that P3 is started as an open source effort, as well as to better understand some of the P2 conversations, I've started learning Verilog (and CPU design). I finally got around to buying the DE0-Nano, which will help a lot. However, I already know I'm going to have a lot of questions. So, where would be the best place to ask them?

Also, to start things off, I'm particularly interested in understanding instruction pipeline designs. I've looked at the opencores site, but I need something more focused on the topic, with documentation. Any suggestions?

rod1963

Learning Verilog(or VHDL) and learning CPU design are two different things. Learn the Verilog first then you will be able to dissect various 32bit open core designs quite easily.

In terms of where to go try Altera's forum.

And here's a freebie from digilent - a sample from the book Introduction to Digital Design" by Richard E. Haskell & Darrin M. Hanna

http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,729,744&Prod=LBE-IDD

Though the book is geared to Xilinx you can use most of it for Quartus. If you like the sample I'd probably buy the book.

Seairth

I had a bit of VHDL knowledge going into this, so the Verilog has been fairly straight forward, so far. For application, I've currently been focusing on "simple" modules (e.g. shift registers, basic ALUs, etc.), but know I need to start building up to more complex designs.

I'll take a look at the book. Also, the J1 Forth CPU (http://www.excamera.com/sphinx/fpga-j1.html) that was mentioned in another post recently has been very helpful. While there is no pipelining, the basic CPU concepts are very easy to understand.

Cluso99

Open cores www.opencores.com has a wealth of open designs from ALUs, peripherals, all the way up to complete cpu cores.
Both Altera and Xilinx have example code.
I found "The Verilog Golden Reference Guide" by "Doulos" www.doulos.co.uk from a link on this forum a month or two ago. Haven't had time to read it yet though.
www.fpga4fun.com may also contain some useful info.

nutson

A great resource for well documented projects with Verilog source code is http://people.ece.cornell.edu/land/courses/ece4760/FinalProjects/

Seairth

I'm putting this here for anyone else who gets the DE0-Nano and decides to follow the "my first fpga" tutorial in the user manual while waiting to play with the P2 goodiness. There is an error in Section 6.7 (Create a Default TimeQuest SDC File), Step 3. The instruction states that you should enter:

create_clock -period 20.000 -name CLOCK_50
derive_pll_clocks
derive_clock_uncertainty

However, it should be:

create_clock -period 20.000 CLOCK_50
derive_pll_clocks
derive_clock_uncertainty

A few additional notes:

• Instead of "20.000", you could also enter "50.000MHz" to be more consistent with the rest of the project
• You can still include a "-name" with some value, but that "CLOCK_50" must at the end of the command, as it indicates which pin to associate the clock to.

nutson

To react on your original question: google for "305formalreport.pdf" that describes the design af a pipelined MIPS like processor complete with Verilog code

Seairth

nutson wrote: »

To react on your original question: google for "305formalreport.pdf" that describes the design af a pipelined MIPS like processor complete with Verilog code

Thanks! This is exactly what I'm looking for!

KC_Rob

Seairth wrote: »

I'll take a look at the book. Also, the J1 Forth CPU (http://www.excamera.com/sphinx/fpga-j1.html) that was mentioned in another post recently has been very helpful. While there is no pipelining, the basic CPU concepts are very easy to understand.

The beauty of a stack micro -- simple yet efficient.

I'll mention two books. You're probably far enough along that you don't need it, but "Verilog by Example: A Concise Introduction for FPGA Design" by Blaine Readler is an excellent primer. I have looked at but have not yet read "Advanced Chip Design, Practical Examples in Verilog" by Mr Kishore K Mishra, but it appears to be very thorough and gets good reviews.

Ale

I am also still learning Verilog. I am finishing my take at the 6809, you can visit it at http://opencores.org/project,6809_6309_compatible_core. That is not my first cpu, more like #25 (from bit-serial, to nibble, to cog-like, forth...), and there is a lot that I don't know or don't understand fully yet. (it is for my taste slow and complicated but I reached one of the goals, that it runs at 40 MHz . It has some mistakes, it is difficult to visualize the whole, I need to work on it.
Things like... should I use asnyc muxes or sync ones and things like that.

One simple and clear example of a pipelined processor that you can understand in like 30 mins (if you know nothing about mips), is http://opencores.org/project,mips_16. I also asked myself how exactly a pipeline processor works, and at least in its simplest form, it works as I thought, but the implementation escaped me till I found this, maybe worth a look.

I bought this book: "The Verilog® Hardware Description Language" Donald Thomas und Philip Moorby von Springer, it was really helpful. I understood the basic concepts on how the hw works.
I'd like a book more oriented on real implementation practices now, but not a >100$ monster...

Have fun

We could have a nice verilog sub-forum here

Ale

this link is also quite ground-level : http://www.dc.uba.ar/materias/disfpga/2010/c1/descargas/TechXclusive%20Creating%20Embedded%20Microcontrollers.pdf

Seairth

I've been thinking of setting up a blog (on this site) focused on learning Verilog, CPU design, etc. This blog would:

• Help me understand what I am learning (i.e. I don't really understand it until I can teach it)
• Link to various forum conversations concerning cpu design (both for the current P2 stuff and for future P3 stuff)
• Link to various external resources (starting with the ones mentioned in this thread) that people may find helpful.
• Try to cover CPU design in general, with an emphasis on propeller-style designs (i.e. no discussion of interrupts)

This might be a bit ambitious, but I feel like others in my position (new to CPU hardware design) would find it helpful (particularly if P3 goes "open source"). And there isn't really a good place for this on the forums. So, would others find this useful, or is there a different way and/or location that something like this should be done?

(Note: do not expect any revelations of the internal workings of the P2, or other Parallax products, unless Parallax itself starts providing that information. If I post anything that looks P2-specific, it'll be entirely speculative and will be marked as such.)

David Betz

Seairth wrote: »

I've been thinking of setting up a blog (on this site) focused on learning Verilog, CPU design, etc. This blog would:

• Help me understand what I am learning (i.e. I don't really understand it until I can teach it)
• Link to various forum conversations concerning cpu design (both for the current P2 stuff and for future P3 stuff)
• Link to various external resources (starting with the ones mentioned in this thread) that people may find helpful.
• Try to cover CPU design in general, with an emphasis on propeller-style designs (i.e. no discussion of interrupts)

This might be a bit ambitious, but I feel like others in my position (new to CPU hardware design) would find it helpful (particularly if P3 goes "open source"). And there isn't really a good place for this on the forums. So, would others find this useful, or is there a different way and/or location that something like this should be done?

(Note: do not expect any revelations of the internal workings of the P2, or other Parallax products, unless Parallax itself starts providing that information. If I post anything that looks P2-specific, it'll be entirely speculative and will be marked as such.)

I'd kind of like to learn Verilog and CPU design by making a clone of the P1. I think jazzed has already done that but I'm not sure if he got to the point of running it on an FPGA.

Seairth

David Betz wrote: »

I'd kind of like to learn Verilog and CPU design by making a clone of the P1. I think jazzed has already done that but I'm not sure if he got to the point of running it on an FPGA.

That would be a good exercise/goal. I'm not sure what Parallax would think of someone creating a P1 clone on their own site, though.

Also, somewhat related, I should point out that I only intend to cover CPU design as far as FPGA soft cores. As I'm not really interested in making my own ASICs, I won't be focusing on that aspect of CPU design.

David Betz

Seairth wrote: »

That would be a good exercise/goal. I'm not sure what Parallax would think of someone creating a P1 clone on their own site, though.

Also, somewhat related, I should point out that I only intend to cover CPU design as far as FPGA soft cores. As I'm not really interested in making my own ASICs, I won't be focusing on that aspect of CPU design.

I'm only interested in FPGAs myself.Making a P1 clone would be a learning exercise and not intended to compete in any way with what Parallax is doing. Just want to create a simple platform for playing with ideas.

Ale

The P1 has several advantages over more traditional RISC processors:

. Small memory from where instructions are fetched (fits a few block-rams)
. Very orthogonal instruction set with no surprises
. 4 clocks per instruction allow to easily do fetch, decode, exec and writeback
. Instruction encoding (effects) help with execution

It is not trivial but simple and very elegant. I should give it another try too

David Betz

Ale wrote: »

The P1 has several advantages over more traditional RISC processors:

. Small memory from where instructions are fetched (fits a few block-rams)
. Very orthogonal instruction set with no surprises
. 4 clocks per instruction allow to easily do fetch, decode, exec and writeback
. Instruction encoding (effects) help with execution

It is not trivial but simple and very elegant. I should give it another try too

Actually, in thinking about it more, the main thing I wanted to play with was adding hub execution but Chip was nice enough to do that for us in P2! Thanks Chip!

Ale

If the condition codes are moved to the highest bits in the opcode, then LMM code would benefit from longer constants

David Betz

Ale wrote: »

If the condition codes are moved to the highest bits in the opcode, then LMM code would benefit from longer constants

True but we don't even need LMM code anymore with P2. :-)

Ale

The bemicro cv is available again . I am ordering a couple.