P2 shrink (28nm / 40nm) and how to collect US $3,200,000
Ramon
Posts: 484
Many of you heard this, but when we were last synthesizing our Prop2 core, I asked the synthesis guy to run it in a 40nm process, just to see how fast it would go. It closed timing, no problem, at 1GHz, and the cell area was only 0.89 square mm. I think this current Prop2, with all we've added, would probably close timing in 28nm at nearly 2GHz. It's just a matter of a few $100k to prove it, and then about $3M to get it into production (the really expensive part).
Yes, I've already heard. Please, can you give more details? I want to know if $3M is for masks only, or masks + sample wafers? If the second case, how many wafers? Also, what is the wafer size and yield for 28/40nm? I think that 28nm and 40nm are only available on 12 inches wafers, right?
This info was collected from the forum:
P1: die 7.28 sqmm (53 mm2) @ 8 inches wafers (27772 mm2) = 524 dies (yield 76.34%, only 400 working dies)
P2: die 7.68 sqmm (54 mm2) @ 8 inches wafers = 236 dies (last shuttle had reduced number of dies due to wasted area) (expected yield: around 85%)
A have calculated this for a P2 shrink:
P2 (28/40nm) @ 8" wafer (27772 mm2): die ~ 1 sqmm = 27772 dies
P2 (28/40nm) @ 12" wafer (66051 mm2): die ~ 1 sqmm = 66051 dies !!!
Are these numbers wrong? If $3M includes some sample wafers, I think it could be feasible to get a sucessful crowdfunding campaign.
I have been looking at several hardware projects. I have found that hardware that are not finished products (like Arduino boards and other PCB boards) usually have a number of funders around 4000 people. But there are also other hardware projects (usually finished products: pebble or OUYA) that get around 64000 funders.
$3,200,000 USD / 4000 funders = $800 USD/chip (UNFEASIBLE, too high price per chip)
$3,200,000 USD / 64000 funders = $50 USD/chip (using one or two 12" wafers)
So It depends on these parameters:
1) The estimated number of people that will fund the project (BACKERS, 4k~64k?)
2) An attractive PRICE for the reward/pledge (the lower the better)
3) NUMBER OF wafers, size of wafer, and yield (at the end: number of sucessful packaged P2 at US $3,200,000).
4) TIMING: (When to start the campaign?) when P2 gets ready and marketing and production starts. (At the same time of the announcement of P2 180nm so parallax can benefit for free advertisement for it's P2 28/40nm shrink crowdfunding campaign)
Comments
Most likely you would expand memory to fill the area, maybe go more COGs.
But you still haven't addressed the bigger cost issues of tester time, most memories in commercial chips have BIST (built in selftest), and all logic has scan insertion.
There is a lot more to factor in than just mask sets.
(Hypothetical discussion, as the 180nm P2 obviously comes first.)
Would it make sense to shrink to 90nm first?
I'd think 90nm would be cheaper to test and fab than 40nm.
For the next shrink, it may even be too early to choose the feature size, as a lot can happen to fab pricing in 2-3 years. Or am I wrong?
True, it is always a moving target of Mask & NRE Costs, Wafer costs, Wafer run sizes, and working Chips per wafer...
The bigger hurdle between now and then, is how to move the manual-ring design elements, into a more shrinkable form.
There is a LOT of P2 that is not Verilog.
It becomes a combination of NRE costs, Chips per wafer, MOQs and expected sales volumes
Smaller process have higher wafer costs, and also can have higher MOQ, and always have larger NRE.
I wonder if the smart pins could be re-coded in Verilog, instead of hand layout. That would save on design cycle time, but (from memory) Verilog is not quite up to it yet - which issue may dissapear in a year or two, as I see more analog capabilities on SOC's all the time. The LPC4370 has some nice ADC's on it for example, but I doubt those were done in Verilog.