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P2P3?

rjo__rjo__ Posts: 2,114
edited 2014-01-06 16:26 in Propeller 2
I have been secreted away trying to fathom the inner workings of applescriptobjc radio buttons. I am planning to post my Prop2<-->Mac serial terminal in the near future.

My present complaint? I can no longer tell the difference between discussions about the P2 and the P3. I love them both but mixing them together is giving me a migraine.

Help!!!!!
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Comments

  • jmgjmg Posts: 15,175
    edited 2013-12-03 19:19
    To help confuse you some more, I'll add that there is some suggestion to call what ships P3 (given it has morphed some way from the original P2), and that makes what will ship next P4, (or P5 ? ) ;)
  • T ChapT Chap Posts: 4,223
    edited 2013-12-03 19:36
    P3 rolls off the tongue better, more easily remembered as a marketing point. Also, when history looks back on the company and product evolution, it will be more interesting to have skipped the P2, it adds mystery, like skipping floor 13. Why did they skip it? Because they felt like it.
  • Ym2413aYm2413a Posts: 630
    edited 2013-12-03 19:56
    Regardless of whatever they call the chip. I'm personally going to stick with the version-II idea in naming my code. : ]
  • pedwardpedward Posts: 1,642
    edited 2013-12-03 21:20
    I have declared that P3 shall be 64 bits, no more, no less. P2 is an extension of the P1 32 bit instruction set. There, I've cleared that up. :)

    Seriously, my rationale is this: The P2 is called the P8X32C, because it's 8 cores and 32 bits, 3rd rev.

    The P3 will be a P8X64A or somesuch because it has 64 bit operands.
  • Roy ElthamRoy Eltham Posts: 3,000
    edited 2013-12-03 21:49
    Why can't P3 be 40 or 48bits? No need to go all the way to 64bit.
  • jmgjmg Posts: 15,175
    edited 2013-12-03 22:34
    Roy Eltham wrote: »
    Why can't P3 be 40 or 48bits? No need to go all the way to 64bit.

    Engineering says 40/48/56 bits could be fine, but Marketing would not cope with anything less than 64 bits.

    Of course, even 64 bits is somewhat elastic, and some 8 bit controllers with a few 16 bit opcodes, claim to be 16 bit.

    The P2 already has some 64 bit operands and results, so it can claim to be somewhat 64 bit capable already.

    Where 64 bit has practical use, is in intermediate value for scaling. Res = A * B / C
  • potatoheadpotatohead Posts: 10,261
    edited 2013-12-03 22:53
    Well, blow their minds and make the thing 61 or 67 bits then. Everybody has a field day!
  • Roy ElthamRoy Eltham Posts: 3,000
    edited 2013-12-03 23:14
    In the Prop architecture, the thing these guys want to be 64bit is the instruction size (and thus cog memory/register size). Going to 64bit means taking up a lot of space for stuff we probably don't need.

    With 40bit, the COG instruction/register space could be 16 times larger, with 48bits it could be 256 times larger. Although I think with a 48bit instruction size, it would make sense to have S and D be 16bits each, and add 2 bits to the opcode field it would be cleaner. 64k instructions/registers ( 384KB (6 bytes per register) ) per cog would be pretty deluxe. HUB memory will need to be pretty darn large, probably something like 4MB at least.
  • WBA ConsultingWBA Consulting Posts: 2,934
    edited 2013-12-03 23:36
    I was trying to make sense of the latest 5 pages of the Propeller 2 Update thread, but was unable to find anything that gave any status as to an actual P2 chip becoming a reality. I wish there was an announcement posting on the forums that was updating once a week with the current status of the P2.
    As much as the thread seems to be bouncing all over and venturing further and further away from the P1, I wonder if there is any reason to call this new chip a Propeller at all. Is it really the next version of Propeller 1 or something mostly different?
  • Heater.Heater. Posts: 21,230
    edited 2013-12-04 00:06
    WBA Consulting.
    I wish there was an announcement posting on the forums that was updating once a week with the current status of the P2.
    As far as I can tell there has been a P2 status update every 2 minutes on the P2 blog thread for the past couple of weeks!

    Also as far as I can tell the P2 still looks like a P1 with an order of magnitude more speed and HUB RAM and a lot more pins.

    Of course a ton of new features and instructions have been added but I think you can still ignore most of that and program it with a P1 mindset.

    I'm sure Ken would like some stable status reports as well.
  • jmgjmg Posts: 15,175
    edited 2013-12-04 00:26
    Roy Eltham wrote: »
    In the Prop architecture, the thing these guys want to be 64bit is the instruction size (and thus cog memory/register size). Going to 64bit means taking up a lot of space for stuff we probably don't need.

    With 40bit, the COG instruction/register space could be 16 times larger, with 48bits it could be 256 times larger. Although I think with a 48bit instruction size, it would make sense to have S and D be 16bits each, and add 2 bits to the opcode field it would be cleaner. 64k instructions/registers ( 384KB (6 bytes per register) ) per cog would be pretty deluxe. HUB memory will need to be pretty darn large, probably something like 4MB at least.

    Ah, you are talking about opcode size.
    Seems to me there will always be some waste.
    If you default variable size to 32 bits, with some 64 bit double-size VAR, then Data nicely fills COG memory, but opcode=32 bit.

    If you nudge that to 40 bits, because VAR data is still 32 bits, now COG memory storing opcodes is 100% used, but COG memory storing Data is only 32 bit, so wastes 20% -. (or do you add a Boolean Var space, like the 8051 has ?)

    Or you can make it more Harvard like, with 40/48 bit opcode space and 32/64 bit data arrays, and now no memory is wasted, but you have lost self modifying code....or made it clumsier.
  • Phil Pilgrim (PhiPi)Phil Pilgrim (PhiPi) Posts: 23,514
    edited 2013-12-04 00:26
    heater wrote:
    Also as far as I can tell the P2 still looks like a P1 ...
    ... albeit less and less so about every two minutes. Executing directly from the hub? Is it still a Propeller? Maybe it should be called the BH2 instead. :) (Sorry, Bill!)

    -Phil
  • ozpropdevozpropdev Posts: 2,793
    edited 2013-12-04 01:14
    P1 vs P2

    Anyone familiar in programming P1 can switch to a P2 without having to start at Page 1 in the manual.
    Most of the instructions that you would be used to in P1 are there in P2.
    The opcodes might be different but the operation is the same.
    You still only have 512 longs of COG ram (-12 regs) so nothing really different there.
    The transition from P1 to P2 PASM is not as steep a learning curve as people may think.
    Sure there are differences in the Peripheral stuff but the fundamental COG concept remains.

    I have found the experience of coming from P1 to P2 quite painless.

    From a "virtual P2 users" perspective, the "look and feel" of P1 is definitely present in P2.
    P2 is definitely a PROPELLER

    DONT PANIC people!

    We are so close.

    Ozpropdev :)
  • potatoheadpotatohead Posts: 10,261
    edited 2013-12-04 06:15
    I second this.
  • rod1963rod1963 Posts: 752
    edited 2013-12-04 10:03
    With all the Prop gurus interchanging P2 and P3 specs and demanding their pet ideas be included, who knows what is what anymore.

    Others are now banging the drums for a kickstarter funded P3.

    It's all getting more cloudy and Silicon Valley vaporwore like.

    Personally I would like to see a real P2 along with a functional GCC compiler and library so the rest of us non-gurus could actually use it. Until then I'll stick with the Cortex M4 and Pic32.
  • WBA ConsultingWBA Consulting Posts: 2,934
    edited 2013-12-04 12:55
    Heater. wrote: »
    As far as I can tell there has been a P2 status update every 2 minutes on the P2 blog thread for the past couple of weeks!

    I would be very hesitant to call the consistent updates on features and the debates contained within a "status update". If I handled my project reports in the same manner, I would be setting myself up for a clear path of demotion. The development and marketing of this chip is a crucial business avenue for Parallax and should be treated as such. Due to Parallax's effort to provide an "open" nature of this process, I would expect there would be an update every 2 weeks on key items of the development, foundry run timeline, key specs, FGPA testing progress, etc. Instead, the Update Blog has turned into a 3 year long monstrosity of a thread that is impossible to comprehend except by those on it daily as part of the process.

    I looked back at the first post to get the start date and caught this comment while there:
    ... if it takes roughly 1 year with a design team of 20 (about 41k man hours), we are ahead of schedule at 5 years out with a design team of 2 individuals (about 21k man hours). That's NOT to say that it will take another 5 years by any means, fortunately we have the luxury of not having 'too many cooks in the kitchen', but realistically we could be looking at this time next year.

    Maybe I am venting because I feel the longevity of my beloved Propeller 1 could be put at risk depending on the outcome of the P2 timeline. Anyhow, here's my Propeller 2 Countdown Timer. I hope it's attainable. :innocent:
  • Dave HeinDave Hein Posts: 6,347
    edited 2013-12-04 13:15
    It's interesting that you picked April Fools Day for the release date. :)
  • KC_RobKC_Rob Posts: 465
    edited 2013-12-04 13:20
    ozpropdev wrote: »
    DONT PANIC people!

    We are so close.
    Are you sure about that? Honestly, I'm skeptical that there will be a design-in-ready part available in 2015. Based on history and past hyperbole, I feel justified in thinking that way.

    I'm in camp with WBA, Phil, rod1963, et al. - P2 does seem a ways away from P1; if not in type, then certainly in scale. Regardless, it's a dream right now - we'll see what P2 is and how it fits in when there actually is a finished chip (or even a finished specification). In the meantime, I am more concerned about P1 and how all this might affect it.
  • jmgjmg Posts: 15,175
    edited 2013-12-04 13:33
    KC_Rob wrote: »
    In the meantime, I am more concerned about P1 and how all this might affect it.

    ??

    P2 has already helped P1 significantly, it has helped seed the GCC development.
  • KC_RobKC_Rob Posts: 465
    edited 2013-12-04 13:39
    jmg wrote: »
    ??

    P2 has already helped P1 significantly, it has helped seed the GCC development.
    That couldn't have been done anyway? Don't buy it. Moreover, clearly P2 development itself has been a huge drain on Parallax resources so that much now hinges on it, including quite possibly P1's future.
  • Dave HeinDave Hein Posts: 6,347
    edited 2013-12-04 13:51
    It's a fact that the GCC development, which was started about 2.5 years ago was targeted for P2. It switched to P1 after a few months when it was realized that P2 would not be available for a while. So P1 may not have had GCC if P2 had come out earlier.
  • KC_RobKC_Rob Posts: 465
    edited 2013-12-04 14:02
    Dave Hein wrote: »
    It's a fact that the GCC development, which was started about 2.5 years ago was targeted for P2. It switched to P1 after a few months when it was realized that P2 would not be available for a while. So P1 may not have had GCC if P2 had come out earlier.
    Nonetheless, P2 was not required to do that. Once it was realized that GCC for P1 would be desirable, from a marketing standpoint, which should have been and no doubt was some time ago, it could have been made a priority; as could have many other things. And none of this addresses the concerns raised over the potential financial/business consequences of the now already long drawn-out (over-) development of P2; it's only marginalia.
  • David BetzDavid Betz Posts: 14,516
    edited 2013-12-04 14:02
    Dave Hein wrote: »
    It's a fact that the GCC development, which was started about 2.5 years ago was targeted for P2. It switched to P1 after a few months when it was realized that P2 would not be available for a while. So P1 may not have had GCC if P2 had come out earlier.
    I'm not sure we actually ever got started on P2 because there wasn't any hard information about the instruction set at that time. I remember we asked you to implement as much as possible in your simulator but I don't think we ever got to generate any P2 code from GCC before switching to P1. How is your simulator doing? Have you been updating it as the P2 instruction set has changed?
  • bruceebrucee Posts: 239
    edited 2013-12-04 14:03
    When I was HP we had a saying--

    There comes a time in every project, when its time to shoot the engineers ship something.

    and no I was on the engineering side, not marketing.
  • KC_RobKC_Rob Posts: 465
    edited 2013-12-04 14:06
    brucee wrote: »
    When I was HP we had a saying--

    There comes a time in every project, when its time to shoot the engineers ship something.

    and no I was on the engineering side, not marketing.
    LOL! I posted something about this in another thread just the other day. One place I worked at even had a sign in the engineering area that said something along these lines. :)
  • KC_RobKC_Rob Posts: 465
    edited 2013-12-04 14:08
    David Betz wrote: »
    I'm not sure we actually ever got started on P2 because there wasn't any hard information about the instruction set at that time. I remember we asked you to implement as much as possible in your simulator but I don't think we ever got to generate any P2 code from GCC before switching to P1.
    Safe to say, then, that the prospect of a P2 wasn't really required to start development on GCC tools for P1.
  • Dave HeinDave Hein Posts: 6,347
    edited 2013-12-04 14:18
    David Betz wrote: »
    I'm not sure we actually ever got started on P2 because there wasn't any hard information about the instruction set at that time. I remember we asked you to implement as much as possible in your simulator but I don't think we ever got to generate any P2 code from GCC before switching to P1. How is your simulator doing? Have you been updating it as the P2 instruction set has changed?
    Spinsim has a -t option that enables the P2 mode. It supports the P1 instructions, but with the P2 code values as defined about 2 years ago. It also simulates the larger RAM, CLUT, PTRX, INDX, the deeper instruction pipeline and the various new jump instructions. I haven't updated it since then. I might work on it again when the P2 design is finalized and the documents are updated.
  • jmgjmg Posts: 15,175
    edited 2013-12-04 14:20
    KC_Rob wrote: »
    Safe to say, then, that the prospect of a P2 wasn't really required to start development on GCC tools for P1.

    I did not say it was required, I said it seeded - clearly GCC is there now, and P2 is not.
    The prospect of P2 galvanized action. Certainly a good thing for P1.
    KC_Rob wrote: »
    Moreover, clearly P2 development itself has been a huge drain on Parallax resources so that much now hinges on it, including quite possibly P1's future.

    Only if Parallax go broke.
    Salaries have to be covered, but they are not large external costs. Large external costs are what send companies broke.

    P1 is a proven die, they can order more at very low risk, and almost no man-hour cost.
    I really do not see this imagined connection between P2 design, and P1 future ?
  • KC_RobKC_Rob Posts: 465
    edited 2013-12-04 14:38
    jmg wrote: »
    I did not say it was required, I said it seeded - clearly GCC is there now, and P2 is not.
    The prospect of P2 galvanized action. Certainly a good thing for P1.
    Yes, a good thing for P1 that could have (and should have) been done regardless.
    Only if Parallax go broke.
    Salaries have to be covered, but they are not large external costs. Large external costs are what send companies broke.
    There are other reasons, like products that simply don't sell as expected (or simply having no viable product at all).
    P1 is a proven die, they can order more at very low risk, and almost no man-hour cost.
    I really do not see this imagined connection between P2 design, and P1 future ?
    Are P1 sales growing or shrinking? If P2 fails, after all this time and money, and P1 sales have been trending down anyway (in part thanks to inattention), what happens to Parallax? What if there is no P2 until, say, 2017?

    It's really quite easy to see the potential connection - takes no trouble at all.
  • David BetzDavid Betz Posts: 14,516
    edited 2013-12-04 14:48
    jmg wrote: »
    I did not say it was required, I said it seeded - clearly GCC is there now, and P2 is not.
    The prospect of P2 galvanized action. Certainly a good thing for P1.
    Well, my personal story about GCC for the Propeller is a little different. It started with me asking Ken Rose if he was interested in working on a spare time project to write a code generator for GCC that targeted the Propeller. At the time that meant P1. I mentioned this idea to Ken Gracey and he seemed interested in having Parallax participate in the project. He may himself have been motivated by a desire to have GCC for P2 but that wasn't my reason for proposing the project. Also, talk of porting GCC to the Propeller certainly predates my conversations with Ken Rose but that is where my involvement began.
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