CTRA, CTRB in two cogs to access the same pin

TCP71 · 2013-11-19 15:15

This is probably a basic and dumb question, but please bear with me. I have two input pins on my prop and I want a pulse on either one of them to trigger a single output pin as quickly as possible. I am already using the ctra/ctrb (with an intermediate pin to keep the polarity right) in a single cog to make it work, but when I try to activate two cog's registers to take the two input pins and make the intermediate or output pin change state, neither has any affect anymore. The code for the cogs is this:

PUB CTRReg1

dira[ETTOut]~~ 'Output
dira[PPSspare]~~
dira[B1TB]~

Ctra := %01011 << 26
Ctra |= PPSspare << 9
Ctra |= B1TB

Ctrb := %01011 << 26
Ctrb |= ETTOut << 9
Ctrb |= PPSspare
repeat
pause(100)

PUB CTRReg2

dira[ETTOut]~~ 'Output
dira[PPSspare]~~
dira[B2TB]~

Ctra := %01011 << 26
Ctra |= PPSspare << 9
Ctra |= B2TB

Ctrb := %01011 << 26
Ctrb |= ETTOut << 9
Ctrb |= PPSspare
repeat
pause(100)

The ETTOut is the single pin I need to mimic the two input pins, B2TB and B1TB, with PPSspare being the intermediate pin that is in opposite polarity to the required output. I call both CTRReg1 and CTRReg2 using the cognew command. Any help would be appreciated.

kuroneko · 2013-11-19 15:50

You can't use the same PPSpare pin for both. If e.g. B1TB is idle (low) PPSpare is high therefore blocking anthing done by B2TB. Also, code postings are best wrapped in [noparse]

[/noparse] tags.

TCP71 wrote: »

... and I want a pulse on either one of them to trigger a single output pin as quickly as possible.

Beau Schwabe · 2013-11-19 16:03

"You can't use the same PPSpare pin for both. If e.g. B1TB is idle (low) PPSpare is high therefore blocking anthing done by B2TB" - Unless that's the functionality that he is looking for. In which case B1TB and B2TB could be considered a gated AND function, while PPSpare is 180 out of phase and ETTOut is true to B1TB and B2TB.

I did notice that the "pause(100)" seems unnecessary and at least one counterB section is redundant.

CON
        _clkmode = xtal1 + pll16x                                               'Standard clock mode * crystal frequency = 80 MHz
        _xinfreq = 5_000_000


ETTOut = 0      'OUTPUT
PPSspare = 1
B1TB = 2        'Input Pin
B2TB = 3        'Input Pin

Var

long    Stack1[15]
long    Stack2[15]



PUB TESTing

cognew( CTRReg1, @Stack1)
cognew( CTRReg2, @Stack2)


        
PUB CTRReg1

'dira[ETTOut]~~ 'Output
dira[PPSspare]~~
dira[B1TB]~

Ctra := %01011 << 26
Ctra |= PPSspare << 9
Ctra |= B1TB

'Ctrb := %01011 << 26
'Ctrb |= ETTOut << 9
'Ctrb |= PPSspare

repeat



PUB CTRReg2

dira[ETTOut]~~ 'Output
dira[PPSspare]~~
dira[B2TB]~

Ctra := %01011 << 26
Ctra |= PPSspare << 9
Ctra |= B2TB

Ctrb := %01011 << 26
Ctrb |= ETTOut << 9
Ctrb |= PPSspare

repeat

TCP71 · 2013-11-20 07:24

Thanks. I will try it with separate intermediate pins as my intent is to have just one output follow the two inputs. If separate inversion pins are required, I can make that work. The repeat and pause are just to keep the cogs going for now. I will add code for them a bit later. Thanks.

TCP71 · 2013-11-20 09:24

Using a separate pin in each cog to do the intermediate stage worked. Thank you. I tried with the "redundant" counter B section removed, but it didn't work. I assume because each input --> intermediate -->output section is running in its own cog, simply dropping the CTRB and dira{ETTout) no longer allowed that cog to access the output pin.

CTRA, CTRB in two cogs to access the same pin

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