Building relocatable code snippets
ozpropdev
Posts: 2,793
Hi All,
Following on from Heaters idea on re-entrant code snippets
See http://forums.parallax.com/showthread.php/150541-Recursive-Reentrant-code-in-COG
It occurred to me that it would be very easy to run 4 x byte code interpreters in 1 cog.
The only problem is that the code snippets are aligned to a single address(codebase).
By placing a simple header in front of all snippets with some count and offset values, the snippets
can be loaded and then relocated before execution. All snippets are compiled with a 0 base address.
The attached code is a simple example of this technique.
The target platform is the DE2 board. (Uses LEDS as status etc.)
Maybe this could be used to combine OBEX code snippets.
Following on from Heaters idea on re-entrant code snippets
See http://forums.parallax.com/showthread.php/150541-Recursive-Reentrant-code-in-COG
It occurred to me that it would be very easy to run 4 x byte code interpreters in 1 cog.
The only problem is that the code snippets are aligned to a single address(codebase).
By placing a simple header in front of all snippets with some count and offset values, the snippets
can be loaded and then relocated before execution. All snippets are compiled with a 0 base address.
The attached code is a simple example of this technique.
The target platform is the DE2 board. (Uses LEDS as status etc.)
Maybe this could be used to combine OBEX code snippets.
Comments
LOADSNIP D,S
This would load a snippet from hub ram to cog ram.
By using a dedicated unused opcode as a end of snippet marker to set length.
RELOC D,S
Relocates last loaded snippet using the simple header technique?
Thoughts?
Some time ago I proposed to Chip.
COGLOAD
like COGINIT --- But instead of second parameter PLACE and LENGHT to load.
COGLOAD HubAddres, CogAddres-Lenght
Yes, RELOC would be tricky but maybe LOAD is possible.
That's the sort of thing I was thinking of.
Does what you want a load instruction to do, just as fast as a load instruction could :-)
(I've used this in some of my p2 tests - works great)
Thanks Bill
Very elegant, compact and fast! I have used this too in some of my P2 stuff.
What made me mention this idea is when you start introducing multi-tasking into the mix this
technique starts to grow in size when taking into consideration 4 x tasks, variable length code and
assorted source addresses. Also with only 2 IND and 2 PTR registers, conventional register indexing has to
be employed to achieve the same result.
As small as possible code being the mission. (Larger snippets - I'm greedy )
Cheers
Brian
I agree that for some cases a LOAD instruction would be nice... but personally (your mileage may vary) I don't know if it is worth the transistors - perhaps there are more general purpose improvements that would be used in more code that would make better use of the transistors?
I hope to find time to try your invaders soon... been too busy with some other projects so far