Hei Leon, did you buy by arrow.com ? Don't they have a UK site ?... (I thought they had one in Germany too...).. I'm going to get one of those kits...
Seems like a bunch of people are buying these boards. Has Chip said he'll make a P2 configuration available for it or is this just a way to have fun with FPGAs?
Hei Leon, did you buy by arrow.com ? Don't they have a UK site ?... (I thought they had one in Germany too...).. I'm going to get one of those kits...
I had problems ordering from Arrow with my debit card, so I used Verical.
Arrow has a UK subsidiary but kits are only available direct from the USA, AFAIK. It might be worth asking your local branch if they can supply it.
David,
Chip hasn't mentioned that he is doing anything with them, I'd have thought that he has enough on his plate. It's just a cheap way to get into the latest 28 nm FPGA technology. The chips themselves aren't even available, yet.
Chip hasn't mentioned that he is doing anything with them, I'd have thought that he has enough on his plate. It's just a cheap way to get into the latest 28 nm FPGA technology. The chips themselves aren't even available, yet.
That's what I thought. I already have a number of FPGA boards and very little time for playing with Verilog. I guess I should resist the temptation to buy this new cool board! :-)
DHL has turned up with the kit, but I didn't have the cash for the duty and VAT, and the delivery man couldn't take a card payment. I paid the amount owing on-line, and arranged a redelivery for tomorrow. It's a pity as I had a simple VHDL program ready for initial testing that lights an LED when one of the buttons is pressed (I can't get on with Verilog)..
DHL has turned up with the kit, but I didn't have the cash for the duty and VAT, and the delivery man couldn't take a card payment. I paid the amount owing on-line, and arranged a redelivery for tomorrow. It's a pity as I had a simple VHDL program ready for initial testing that lights an LED when one of the buttons is pressed (I can't get on with Verilog)..
I'm too lazy to program in VHDL. Too many words to type! That's why I don't do Cobol either. :-)
I think if everyone could get on board with a single board, it might make sense to migrate. And then Chip would only have to support just that board.
It makes sense to move up to 28nm chips for the next leg in the development... and migrating now vs later might actually save Chip some work, if we could all agree. I need another cog or two and more RAM... I don't mind shelling out the money if Chip is going to stick with the DE2-115, but if he is going to migrate later... let's do it now... or in the near future, when the plate is only half full:)
I think if everyone could get on board with a single board, it might make sense to migrate. And then Chip would only have to support just that board.
It makes sense to move up to 28nm chips for the next leg in the development... and migrating now vs later might actually save Chip some work, if we could all agree. I need another cog or two and more RAM... I don't mind shelling out the money if Chip is going to stick with the DE2-115, but if he is going to migrate later... let's do it now... or in the near future, when the plate is only half full:)
One problem with everyone going to a single board is that some people already have the DE0-Nano and the DE2-115 and may not want to buy another FPGA board.
I just received a Cyclone V SOC board http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=167&No=816. The board is surprisingly small, half the size of the DE2-115, all large IC's are BGA now (the VGA connector seems very large suddenly). Plan is to port my P1 emulator to this board, and use the internal RAM as multiport VGA. Need to download and install the latest Quartus first, only version 13.0 supports the Cyclone V family. Also ordered an HSMC breakout board from Bitec http://www.bitec.ltd.uk/hsmc_proto.html to interface with P1 boards.
I understand the urge to go with the newest technology and bigger FPGA's, do it myself, Cyclone V has many advantages, especially lots of high speed internal RAM. But it would be unwise to let down the board members that invested in DE0-nano and DE2-115 boards, they will drop out and not return.
I doubt people like David, Cluso, Ariba or potatohead would drop anytime soon. they have been here forever !
I'll probably get the BeMicro board myself.
Edit: A P1 emu ?... very interested . I should continue with mine, too. After I finish the current QuerForth core (Works on the MachXO2-7000 and probably on the 1200 too).
To some extent I guess it depends on how much Chip continues to change the P2 instruction set. If it stabilizes relatively soon and a configuration is made available for the DE0 and DE2 boards then I guess those who have those boards can keep using them even if Chip ports to another FPGA board or two. I'm tempted by the BeMicro myself given its low price but I have to admit that I only bought my DE0-Nano board myself. Parallax was nice enough to send me my DE2-115 to use for PropGCC work.
I have a question about the BeMicro board. I think I saw here that it can only support a single COG like the DE0-Nano. Is it able to support a larger hub memory? If not, what is the advantage other than a slightly lower price?
This Verilog CPU design can execute a limited subset of PASM, but I lost interest when it came to all the nitty-gritty details of getting C and Z flags right. But the basic structure runs at 33 MIPS (100MHZ, 3 clocks / instruction no pipeline )
I have ported the design to several Terasic boards including the DE2-115. Some board members have requested (and received) my source code.
The BeMicro board could only support one COG (the same number of LE's as the DE0-nano) but with 128KB of hub memory.
This Verilog CPU design can execute a limited subset of PASM, but I lost interest when it came to all the nitty-gritty details of getting C and Z flags right. But the basic structure runs at 33 MIPS (100MHZ, 3 clocks / instruction no pipeline )
I have ported the design to several Terasic boards including the DE2-115. Some board members have requested (and received) my source code.
Sounds very interesting! Good luck with your port to the BeMicro board!
The BeMicro board could only support one COG (the same number of LE's as the DE0-nano) but with 128KB of hub memory.
Having the full 128k of hub memory available would be a big plus! I would certainly be willing to invest $49 for that.
Dave , you'are mixing up FPGA boards. I am going to play with the Arrow/Terasic Cyclone V SoCKkit. This has an FPGA with 110k LE's, 500 KB of internal memory and a dual core ARM at 800 MHz.
I am not in favour of pushing the BeMicro, as it would stil yield a single P2 COG solution (although with 128KB hub). If any, the upcoming Cyclone V starter board at $179 could be an lower priced alternative to the DE2-115. It could support 3-4 COG's with full hub memory.
But I feel it is better not to bother Chip with yet another FPGA solution.
This Verilog CPU design can execute a limited subset of PASM, but I lost interest when it came to all the nitty-gritty details of getting C and Z flags right. But the basic structure runs at 33 MIPS (100MHZ, 3 clocks / instruction no pipeline )
I have ported the design to several Terasic boards including the DE2-115. Some board members have requested (and received) my source code.
Is it your plan to eventually make this open source?
Not in the sense that I plan to publish the code. It is very incomplete, and needs a propeller board connected to the FPGA expansion connector with a 12 line bus. You can write PASM as a DAT section in a SPIN loader program that uploads this into the COG register memory, and release the COG reset switch on the FPGA board. If you want to have a copy for fun and laughs drop me PM with a mail address
But I feel it is better not to bother Chip with yet another FPGA solution.
I'd agree, not for tomorrow, but once the P2 is frozen, then Cyclone V needs to be added, most of the work will be in the 'Add Cyclone V' part, and from there, support of both (or more) Cyclone V boards would be logical.
One COG with full HUB is still very useful, and the price makes it widely accessible.
This Verilog CPU design can execute a limited subset of PASM, but I lost interest when it came to all the nitty-gritty details of getting C and Z flags right. But the basic structure runs at 33 MIPS (100MHZ, 3 clocks / instruction no pipeline )
is this a P1, or P2 core ? - it would be interesting to know how many P1 COGs could fit into BeMicro CV, (& what MHz) as the P1 COG is likely to be much smaller.
It is small CPU (1500 LE's) that can execute a subset of the P1 PASM. Nothing more, No pipeline, no hub, no counters, nothing more. I used it to drive other FPGA board resources, example write a 256K16 SRAM output as 800 x 600 VGA bitmap.
If Chip were to support another board, then the $179 would be my choice simply because it would permit more than 1 cog. While the $49 is attractive, we already have the more expensive DE0 for a single cog.
Meanwhile Chip has way too much on his plate atm. The new instruction set is a major improvement.
These new Boards all have DDR Ram while the DE0-Nano and the DE2-115 have just the right SDRAM chip on board (the one that will also work with the real Prop2 chip).
As long as Chip not plans to add DDR support to the Prop2 these new boards make not much sense.
The board comes with a nice short USB cable about 9" long. I expected it to have a test program already installed, like most FPGA boards, but it didn't.
My little test program worked OK, except that the LED is normally on and pressing the button turns it off. It might be useful for anyone else getting one of these kits, so here it is:
-- Simple test program for BeMicro CV kit
--
-- Lights USER_LED0 when Tact1 button is pressed
--
-- USER_LED0 - Pin U1
-- Tact1 - Pin H18
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
ENTITY Test IS
PORT
(
USER_LED0 : OUT STD_LOGIC;
Tact1 : IN STD_LOGIC
);
END Test;
ARCHITECTURE a OF Test IS
attribute chip_pin : string;
attribute chip_pin of USER_LED0 : signal is "@U1";
attribute chip_pin of Tact1 : signal is "@H18";
BEGIN
USER_LED0 <= NOT Tact1;
END a;
It is small CPU (1500 LE's) that can execute a subset of the P1 PASM. Nothing more, No pipeline, no hub, no counters, nothing more. I used it to drive other FPGA board resources, example write a 256K16 SRAM output as 800 x 600 VGA bitmap.
You could stuff 8 of these in BeMicro CV.
I wonder if I could fit one mini-COG in this XuLA-200 board that I've had kicking around for ages? It uses a Xilinx FPGA though.
David, porting a design from an Altera FPGA to Xilinx is more work than loading the Verilog and push "compile". Some redesign and verification may be needed
- M9K memory blocks are different from Xilinx BRAM's .
- Altera PLL's are different from Xilinx DCM's ( Digital Clock manager)
- all Altera MegaFunctions probably have an equivalent in ISE but the devil is the detail
- and last but not least: Quartus is is a smoother development environment than ISE, reason why Xilinx recently has introduced a new tool Vivado
Xilinx has the lead in silicon, but Quartus is the better integrated design and test environment
nice little board. A Spartan 3S200 has some 4200 logic cells (LUTs), it is not bad, and has multipliers ! The MachXO2-7000 that I am using is not as fast, has more logic but no multipliers ... but a 16 cycle booth implementation requires some 140 LUTs... One full COG would probably fit on that board. You can test what I posted on the General forum a while back...
nice little board. A Spartan 3S200 has some 4200 logic cells (LUTs), it is not bad, and has multipliers ! The MachXO2-7000 that I am using is not as fast, has more logic but no multipliers ... but a 16 cycle booth implementation requires some 140 LUTs... One full COG would probably fit on that board. You can test what I posted on the General forum a while back...
Can you post a link to your COG implementation? Is it a complete COG or a subset?
Comments
I had problems ordering from Arrow with my debit card, so I used Verical.
Arrow has a UK subsidiary but kits are only available direct from the USA, AFAIK. It might be worth asking your local branch if they can supply it.
David,
Chip hasn't mentioned that he is doing anything with them, I'd have thought that he has enough on his plate. It's just a cheap way to get into the latest 28 nm FPGA technology. The chips themselves aren't even available, yet.
It makes sense to move up to 28nm chips for the next leg in the development... and migrating now vs later might actually save Chip some work, if we could all agree. I need another cog or two and more RAM... I don't mind shelling out the money if Chip is going to stick with the DE2-115, but if he is going to migrate later... let's do it now... or in the near future, when the plate is only half full:)
I understand the urge to go with the newest technology and bigger FPGA's, do it myself, Cyclone V has many advantages, especially lots of high speed internal RAM. But it would be unwise to let down the board members that invested in DE0-nano and DE2-115 boards, they will drop out and not return.
I'll probably get the BeMicro board myself.
Edit: A P1 emu ?... very interested
This Verilog CPU design can execute a limited subset of PASM, but I lost interest when it came to all the nitty-gritty details of getting C and Z flags right. But the basic structure runs at 33 MIPS (100MHZ, 3 clocks / instruction no pipeline )
I have ported the design to several Terasic boards including the DE2-115. Some board members have requested (and received) my source code.
The BeMicro board could only support one COG (the same number of LE's as the DE0-nano) but with 128KB of hub memory.
I am not in favour of pushing the BeMicro, as it would stil yield a single P2 COG solution (although with 128KB hub). If any, the upcoming Cyclone V starter board at $179 could be an lower priced alternative to the DE2-115. It could support 3-4 COG's with full hub memory.
But I feel it is better not to bother Chip with yet another FPGA solution.
I'd agree, not for tomorrow, but once the P2 is frozen, then Cyclone V needs to be added, most of the work will be in the 'Add Cyclone V' part, and from there, support of both (or more) Cyclone V boards would be logical.
One COG with full HUB is still very useful, and the price makes it widely accessible.
is this a P1, or P2 core ? - it would be interesting to know how many P1 COGs could fit into BeMicro CV, (& what MHz) as the P1 COG is likely to be much smaller.
You could stuff 8 of these in BeMicro CV.
Meanwhile Chip has way too much on his plate atm. The new instruction set is a major improvement.
As long as Chip not plans to add DDR support to the Prop2 these new boards make not much sense.
Andy
The board comes with a nice short USB cable about 9" long. I expected it to have a test program already installed, like most FPGA boards, but it didn't.
My little test program worked OK, except that the LED is normally on and pressing the button turns it off. It might be useful for anyone else getting one of these kits, so here it is:
-- Simple test program for BeMicro CV kit -- -- Lights USER_LED0 when Tact1 button is pressed -- -- USER_LED0 - Pin U1 -- Tact1 - Pin H18 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all; ENTITY Test IS PORT ( USER_LED0 : OUT STD_LOGIC; Tact1 : IN STD_LOGIC ); END Test; ARCHITECTURE a OF Test IS attribute chip_pin : string; attribute chip_pin of USER_LED0 : signal is "@U1"; attribute chip_pin of Tact1 : signal is "@H18"; BEGIN USER_LED0 <= NOT Tact1; END a;- M9K memory blocks are different from Xilinx BRAM's .
- Altera PLL's are different from Xilinx DCM's ( Digital Clock manager)
- all Altera MegaFunctions probably have an equivalent in ISE but the devil is the detail
- and last but not least: Quartus is is a smoother development environment than ISE, reason why Xilinx recently has introduced a new tool Vivado
Xilinx has the lead in silicon, but Quartus is the better integrated design and test environment
it needs a bit of work. Now that the forth core works, I can again spend time in this