No, but one thing they don't mention is that reads are destructive. FRAM devices are designed to automatically do a re-write cycle after a read and, with the much larger number of possible write cycles, that shouldn't be a problem. When powering a FRAM device, there needs to be a tiny bit of power reserve so any pending re-write can be completed. I suspect the internal design takes that into account.
No, but one thing they don't mention is that reads are destructive. FRAM devices are designed to automatically do a re-write cycle after a read and, with the much larger number of possible write cycles, that shouldn't be a problem. When powering a FRAM device, there needs to be a tiny bit of power reserve so any pending re-write can be completed. I suspect the internal design takes that into account.
Thanks for the reply, Mike. While I've looked at FRAM devices before (eg, for data logging), this is the first time I've seen FRAM used as the primary (only) memory in a micro.
No, but one thing they don't mention is that reads are destructive.
I don't think TI have magically created non destructive read, so this claim seems confused.
Virtually Unlimited Write Endurance – 1015 Cycles
Test case
CPU speed @ 8MHz
Both memory options capped @ 12kB/s throughput (typical application)
FRAM will last for 6.6x10^10 seconds
Really ? 10^15/(6.6*10^10) = 15151 - oops, they seem to have overlooked Opcode fetches.
If you can IDLE the core for > 90% of the time, (or can run from RAM ) then you could get large time frames, but a core reading FRAM at 8MHz gives
(10^15/8M)/60/60/24/365 = 3.9637 years. not such a large number now, is it ?
No, but one thing they don't mention is that reads are destructive. FRAM devices are designed to automatically do a re-write cycle after a read and, with the much larger number of possible write cycles, that shouldn't be a problem. When powering a FRAM device, there needs to be a tiny bit of power reserve so any pending re-write can be completed. I suspect the internal design takes that into account.
As far as I can tell these chips work like the old core memories did. A destructive read followed by an immediate rewrite of the data. Biggest difference seems to be the manufacturing process. No more hand feeding thin wires through a tiny ferrite doughnut.
Your link made me wonder why one would think 1,015 cycles is "virtually unlimited".
Turns out it not 1,015 cycles but 1,000,000,000,000,000 cycles.
I just checked the datasheet on the Ramtron FRAM (FM25H20), It claims a tenth as many cycles as the memory described in the link you gave (the Ramtron DS lists 100 Trillion cycles (one fewer zero)).
While the chips I have were samples, I believe some of them have a pretty high retail cost. IIRC, one of the sample chips had a retail price over $20 (this was several years ago).
Your link made me wonder why one would think 1,015 cycles is "virtually unlimited".
Turns out it not 1,015 cycles but 1,000,000,000,000,000 cycles.
I just checked the datasheet on the Ramtron FRAM (FM25H20), It claims a tenth as many cycles as the memory described in the link you gave (the Ramtron DS lists 100 Trillion cycles (one fewer zero)).
While the chips I have were samples, I believe some of them have a pretty high retail cost. IIRC, one of the sample chips had a retail price over $20 (this was several years ago).
Yes, it's 10^15 cycles. (I should have paid more attention when I pasted the text, knowing the formatting would be jacked.)
You're probably right about the cost for that part. The Ramtron (now Cypress) FM25640, which I looked at a few years ago, I think was $3-$4 in low qty.; it's 8KB.
Approx $6 per 256KByte FRAM chips (Fujitsu MB85RS2MT), $75 for a 2MByte module.
Which, if memory serves, looks much more affordable compared to Ramtron prices.
KC_Rob
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Comments
http://www.everspin.com/technology.php
I don't think TI have magically created non destructive read, so this claim seems confused.
Virtually Unlimited Write Endurance – 1015 Cycles
Test case
CPU speed @ 8MHz
Both memory options capped @ 12kB/s throughput (typical application)
FRAM will last for 6.6x10^10 seconds
Really ? 10^15/(6.6*10^10) = 15151 - oops, they seem to have overlooked Opcode fetches.
If you can IDLE the core for > 90% of the time, (or can run from RAM ) then you could get large time frames, but a core reading FRAM at 8MHz gives
(10^15/8M)/60/60/24/365 = 3.9637 years. not such a large number now, is it ?
I believe that Cypress acquired them recently.
As far as I can tell these chips work like the old core memories did. A destructive read followed by an immediate rewrite of the data. Biggest difference seems to be the manufacturing process. No more hand feeding thin wires through a tiny ferrite doughnut.
Your link made me wonder why one would think 1,015 cycles is "virtually unlimited".
Turns out it not 1,015 cycles but 1,000,000,000,000,000 cycles.
I just checked the datasheet on the Ramtron FRAM (FM25H20), It claims a tenth as many cycles as the memory described in the link you gave (the Ramtron DS lists 100 Trillion cycles (one fewer zero)).
While the chips I have were samples, I believe some of them have a pretty high retail cost. IIRC, one of the sample chips had a retail price over $20 (this was several years ago).
You're probably right about the cost for that part. The Ramtron (now Cypress) FM25640, which I looked at a few years ago, I think was $3-$4 in low qty.; it's 8KB.
I'm backing this kickstarter project, which is about to end its funding period, for a FRAM module or single chips:
https://www.kickstarter.com/projects/722032672/non-volatile-4mb-f-ramdisk-for-the-raspberry-pi-ex
Approx $6 per 256KByte FRAM chips (Fujitsu MB85RS2MT), $75 for a 2MByte module.
Which, if memory serves, looks much more affordable compared to Ramtron prices.