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Latest code: Getting DE0 working & Program changes required — Parallax Forums

Latest code: Getting DE0 working & Program changes required

Cluso99Cluso99 Posts: 18,069
edited 2013-10-20 09:49 in Propeller 2
New FPGA code and PNUT.EXE release for 30-Sep-2013

I have changed the thread title to better reflect what is/will be here.

I now have my De0-Nano working with the new code. I have documented this in the first post in the sticky.
http://forums.parallax.com/showthread.php/144199-Propeller-II-Emulation-of-the-P2-on-DE0-NANO-amp-DE2-115-FPGA-boards?p=1145599&viewfull=1#post1145599


Software Changes:
Now I have to get the compiler working with my older code. These are the changes required so far...
  • Change xinfreq = 80_000_000 (was 60_000_000)
  • Monitor start address = $700 (was $70C) - thanks ozpropdev
  • The pnut.exe compiler has changed to reflect the new opcodes, so recompiling older code is required.

Original Post:
I have just tried to download the new FPGA configuration (as posted by Chip a few days ago). It reports that it has programmed OK but when I plug my propplug into the DE0 and run PST it does not run the monitor (maybe it does not recognise the "space"). I tried 19200 baud in case the running at 20MHz was the problem.

I retried the old FPGA configuration and all works as expected.

I then reprogrammed the DE0 again with the new FPGA configuration. No luck.

So I plugged in the Parallax expansion board and also put in the link on the DE0 between pins 3 & 5 (checked against the pic Chip posted originally).
I then connected the Propplug to the new header on the expansion board (looking at the Propplug connector, ground is closest the "Prop Plug" white legend and identified by the square solder pad). Still no luck. I haven't run the expansion board before - I seem to recall was there some issue with the SPI Flash.

Any ideas?
Should the DE0 still work standalone (without the expansion board)? If so, is the link required?

Meanwhile I am scouring the threads in case I have missed something.

Comments

  • ozpropdevozpropdev Posts: 2,793
    edited 2013-10-02 22:10
    Hi Cluso99

    Your post popped after I just submitted mine.
    I'm having the same issue with the monitor.
    If I reset the board from PST using DTR checkbox and press "space" the monitor works.
    I cant launch it from my code though?
  • ozpropdevozpropdev Posts: 2,793
    edited 2013-10-02 22:26
    Hi Cluso99
    The new programs require add-on boards.
    remove the flash chip as well.
    Cheers
    Brian
  • Cluso99Cluso99 Posts: 18,069
    edited 2013-10-02 22:47
    Thanks Brian. I removed the flash and hey presto, it works. Now to look for that DJ 2.5 to 2.1 converter (been using the USB power when DE0 was standalone).
  • Cluso99Cluso99 Posts: 18,069
    edited 2013-10-03 00:39
    ozpropdev: Brian, would you like to post the changes you had to do to get your code recompiling? Here is where I am up to...

    Trying to get my P2 LMM Debugger compiling/working...
    I have changed the xinfreq to 80MHz and the monitor rom start to $70C.

    pnut.exe now complains about no PUB.
  • ozpropdevozpropdev Posts: 2,793
    edited 2013-10-03 00:53
    Hi Cluso

    The changes I had to make to Invaders for it to work in the new FPGA and Pnut.exe were as follows.

    1. XINFREQ change to 80_000_000
    2. The FRQA value for the video generation was recalibrated for 80 MHz from 60 MHz
    3. All WAITVID instructions had the POLVID loops removed before them.
    4. GETMUL and GETDIV also had their POLLING loops removed.
    5. Monitor address changed to $700 from $70C
    6. Changed ORGH directive to $E80 from $18E80.

    That's was all if my memory serves me correctly.

    Cheers
    Brian
  • ozpropdevozpropdev Posts: 2,793
    edited 2013-10-03 01:02
    Cluso99 wrote: »
    pnut.exe now complains about no PUB.

    I have never used PUB in my code, so i'm not aware of that issue?

    Besides, most people I know would also complain about no PUBS! (bars,etc)
  • cgraceycgracey Posts: 14,206
    edited 2013-10-03 02:26
    ozpropdev wrote: »
    I have never used PUB in my code, so i'm not aware of that issue?

    Besides, most people I know would also complain about no PUBS! (bars,etc)

    For PASM programs that ORGH to $E80, use F11 to download. F12 is for Spin2 programs. F10 just loads a single-cog loader at $E80.

    Spin2 is in the new PNUT, but it's not documented yet.
  • ozpropdevozpropdev Posts: 2,793
    edited 2013-10-03 02:35
    Cool!
    Thanks Chip
  • Cluso99Cluso99 Posts: 18,069
    edited 2013-10-03 02:48
    Thanks Chip. I have it working now.

    The problem was I was filling the hub space between $E80-$FFF because I wanted to reserve that space for interprogram mailboxes. So my program started at $1000 hub.

    Does pnut still do Ctl-L (create a listing and output file)? It seems to be broken - hence the missing PUB error. I had been using p2load to load the code and start (coginit) at $1000.
  • cgraceycgracey Posts: 14,206
    edited 2013-10-03 05:57
    Cluso99 wrote: »
    Thanks Chip. I have it working now.

    The problem was I was filling the hub space between $E80-$FFF because I wanted to reserve that space for interprogram mailboxes. So my program started at $1000 hub.

    Does pnut still do Ctl-L (create a listing and output file)? It seems to be broken - hence the missing PUB error. I had been using p2load to load the code and start (coginit) at $1000.

    Use CTRL-M for PASM or CTRL-L for Spin.
  • rjo__rjo__ Posts: 2,114
    edited 2013-10-03 07:33
    The only problem I have had so far with a bare NanoP2 is in running Ariba's SDRam_test code. The monitor works correctly and I ran p2-hello (by?) after
    changing the clock. You have to power cycle the Nano after installing the .jic.
  • cgraceycgracey Posts: 14,206
    edited 2013-10-03 07:46
    rjo__ wrote: »
    The only problem I have had so far with a bare NanoP2 is in running Ariba's SDRam_test code. The monitor works correctly and I ran p2-hello (by?) after
    changing the clock. You have to power cycle the Nano after installing the .jic.

    The SDRAM timing on the latest configuration files is marginal and may not work. Yesterday, I found some obscure settings for the Cyclone IV I/O pins which lengthens delays in and out of the pad, relative to the clock, and that made things very solid. When I get new config files out (hopefully later today), those timing changes will be in them. The adjustment amounts to about 1ns of overlap, which makes all the difference.
  • rjo__rjo__ Posts: 2,114
    edited 2013-10-19 11:44
    First let me thank Doctor Potatohead for my shiny new P2-nano add-on board.

    Of course, the first thing I did was run Prop2-Invaders. :):):):)

    I made the changes to Chip's simple_vga_800X600.spin suggested above and adjusted the frqa_ to $12_000_000 as it is in Invaders.

    This worked ok... except that I have thin color bars filling the right side of the image.

    I have poked around quite a bit trying to figure out exactly where $12_000_000 comes from... no luck.
    Is there an equation or is this an empirical number?

    I have looked at the various ntsc drivers and have no clue what needs to be done to run them at clkfreq of 80_000_000 with the latest .jic for the Nano-P2.
    Anyone have a working example?

    Thanks

    Rich
  • TubularTubular Posts: 4,705
    edited 2013-10-19 13:25
    rjo__ wrote: »
    I have poked around quite a bit trying to figure out exactly where $12_000_000 comes from... no luck.
    Is there an equation or is this an empirical number?
    Rich

    That value is a "frequency tuning word" (long?) that sets the output frequency of counter A to 5.625 MHz. You can hook a scope onto the jumper between pins 3 and 5 of the 26 pin header to observe the counter A output, which is then jumpered back into the FPGA to drive the video generator. The video generator has a 8x PLL circuit, which yields a 45 MHz dot clock for driving the VGA monitor

    The equation is:-
    tuning value = desired CTR output frequency * (2^32) / 80_000_000 hz p2 clock

    (keeping in mind the video circuit has a settable PLL that combines to give the final frequency)
  • rjo__rjo__ Posts: 2,114
    edited 2013-10-19 13:55
    Thanks. At one point I was close... had no idea that the counter frequency was 5.625Mhz).

    I did a search for 5.625MHz in history... and it turns out that 5.625MHz is a frequency step useful for 3D synthetic apertures used by the European Institute for the Protection and Security of the Citizenhttp://ipsc.jrc.ec.europa.eu... different PLLs:)
    If anyone is interested in 3D indoor radar http://d-nb.info/100730880X/34

    I am very interested if anyone has 8bit NTSC working with the new configuration. I have samples that used to run but no longer do. I was in the habit of just dumping useful code into a folder without attribution, so I would have to scratch my head to name an author.

    Rich
  • AribaAriba Posts: 2,690
    edited 2013-10-19 19:35
    Here the simple_VGA_800x600 changed to 80 MHz.
    The dot clock is 40 MHz in my code which is the standard as far as I know. My Monitor is a bit picky and does not like non standard frequencies (like 45Mhz).

    Andy

    PS. I hae a working PAL example but not adapted any NTSC code so far.
    spin
    spin
    simple_VGA_800x600.spin
    2K
  • rjo__rjo__ Posts: 2,114
    edited 2013-10-20 06:13
    Andy,

    That helped a lot. The VGA sample now runs on my cheapo vga projector. So, I don't have to keep changing cables. It also fixes Invaders so I can see it on my projector. The same artifact is there in simple_VGA_800x600.spin... I get nice broad color bars on the left side of the screen and a series of narrow color lines on the right.

    When I do the the calculations for frqa for (to produce ntsc 57.272720MHz) I get a decimal value of 384,350,717.73908... which roughly equates to a hex value of 16E8B9FD(or E). I get video!!! out using P2_NTSC_252x96_8bit_Greyscale_DE0.spin(March 17,2013)tubular?.

    Do we have to use polling before waitvid to make either of these multitasking?
  • rjo__rjo__ Posts: 2,114
    edited 2013-10-20 09:20
    oops...looking a little farther... it is multitasking:)
  • AribaAriba Posts: 2,690
    edited 2013-10-20 09:34
    rjo__ wrote: »
    .....
    Do we have to use polling before waitvid to make either of these multitasking?

    No this is no longer needed with the newest FPGA image. WAITVID switches automatically into polling mode if more than one task is active.
    Be aware: it is not the same for all WAITxxx instructions, WAITCNT needs to be replaced with PASSCNT for example.

    Andy
  • rjo__rjo__ Posts: 2,114
    edited 2013-10-20 09:49
    Thanks... just having too much fun. I know the fancy graphics are really impressive, but I can't tell you how much 8-bit gray scale does for my soul.
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