Prop 2 Serial support for FTDI Fast Serial mode
jmg
Posts: 15,161
I'll start this in a separate thread
The High Speed FTDi devices have a Fast Serial mode, that can clock at 50MHz, and can opto-isolate.
It would be an obvious target, for the new P2 serial module to also support this.
FTDI Fast Serial mode is a 'slave clocked async', in operation
* Prop provides a gated clock (FSCLK) - when Prop is not ready, 'no clock' pauses the FT232H output. (buffers internally)
* FT232H sends @ FSDO a START bit and 8+1 data bits and STOP bit. (in FT232H 9th bit is 0, in FT2232H 9th bit is 1/0)
Data changes after FSCLK _/= and is sampled for P2.RXD on FSCLK =\_
FT232H emits a handshake line FSCTS, H=Ready.
If FT232H is ready, Prop sends @ FSDI Start bit and 8+1 data bits and STOP bit. and the FSCLK signal.
FTDI samples on _/=, so Prop updates P2.TXD on =\_
In operation, FSCTS is checked before eachP2.TXD
Sustained byte rate is appx 13 clocks/byte, as the handshake has slight carry.
Note FSDO and FSDI are separate pins, and operation is Duplex.
To support this, not much additional is needed to the above :
* Ability to run in 9 bit mode
* Ability to Enable a CLK, even in 'Async' mode (this CLK is generated by Prop, up to 50MHz )
( this clock is disabled, when P2 is busy and wants the FT232H to buffer USB data )
ref: See FT232H / 2232H data Fast Opto-Isolated Serial Interface Mode Description
The High Speed FTDi devices have a Fast Serial mode, that can clock at 50MHz, and can opto-isolate.
It would be an obvious target, for the new P2 serial module to also support this.
cgracey wrote:- There are two serial subsystems per cog now that operate from 1 clock per bit to 65535 clocks per bit. They do 8N1, both positive and negative polarity, as well as 32N1, negative polarity, for Prop-to-Prop comms. There's also a 4-extra bit ID that can be turned on for automatic message discrimination in the receiver side.
This is all it does:
1) wait for STOP state
2) wait for START state
3) delay 1.5 bit periods
4) sample data bit 0
5) wait 1 bit period
6) sample data bit 1
7) loop 6 times to (5) to get data bits 2..7
8) done, pass received data via SERINA/SERINB, loop to (1).
Note that at (8), RX still reads bit 7, which may be low, and will be followed by the STOP state from the transmitter. The receiver loops to (1) where it retriggers on the next STOP-to-START transition.
FTDI Fast Serial mode is a 'slave clocked async', in operation
* Prop provides a gated clock (FSCLK) - when Prop is not ready, 'no clock' pauses the FT232H output. (buffers internally)
* FT232H sends @ FSDO a START bit and 8+1 data bits and STOP bit. (in FT232H 9th bit is 0, in FT2232H 9th bit is 1/0)
Data changes after FSCLK _/= and is sampled for P2.RXD on FSCLK =\_
FT232H emits a handshake line FSCTS, H=Ready.
If FT232H is ready, Prop sends @ FSDI Start bit and 8+1 data bits and STOP bit. and the FSCLK signal.
FTDI samples on _/=, so Prop updates P2.TXD on =\_
In operation, FSCTS is checked before eachP2.TXD
Sustained byte rate is appx 13 clocks/byte, as the handshake has slight carry.
Note FSDO and FSDI are separate pins, and operation is Duplex.
To support this, not much additional is needed to the above :
* Ability to run in 9 bit mode
* Ability to Enable a CLK, even in 'Async' mode (this CLK is generated by Prop, up to 50MHz )
( this clock is disabled, when P2 is busy and wants the FT232H to buffer USB data )
ref: See FT232H / 2232H data Fast Opto-Isolated Serial Interface Mode Description