Board layout is not a problem - there are plenty of us capable. Manufacturing is not really a problem, just a little harder with FBGA. And Chip knows what hw interfaces we need (for VGA/TV and other analog and the SRAM), all on the one pcb.
The licensing issue is a bigger problem but there are most likely ways around this legally by discussions with Altera. I bet they would come to the party, perhaps even with a discount for the chips. I would be a big publicity bonus for them. Otherwise we ask Xilinx
Re DRAM problems: the high clocks of DRAM DDR2 and DDR3 chips makes it notorious difficult to interface these to general purpose FPGA pins: one of the improvements in the Altera Cyclone V family are the on chip hard DRAM controllers.
@cluso99 and others: a big FPGA board is not simple:
- at least 6 layers (2 power, 4 signal planes)
- EPCQ256 programming device and programming circuit
- 1.1 / 2.5 / 3.3 V supply voltages
- USB blaster circuit (or external JTAG programmer necessary)
I would love the opportunity to play with a P1 /P2 /P3 COG as a module that I can interface myself to FPGA pins, or add new on-chip interface blocks or new instructions to. But that would require Chip to release a COG model as a (closed, encrypted?) module that can be included in a top level Verilog program.
There is a 3rd obvious alternative : Parallax make the PCB.
They are in the business of supplying modules already, this is just a bump in complexity.
Parallax has been so open about P2 development (asking users about features, accepting modifications, given information about shuttle runs and die packaging shipments, offering FPGA binaries, etc ...) that for a while I though we I was part of it. So when I said *we*, I was thinking "Parallax OR the people inside the forum" as opposed to some third company (like terasic, digilentinc, Axelsys, etc...).
The same concept when I said "we ask terasic to make one" : Chip (Parallax) can ask Terasic for a custom board to start P3 development, but also with generic features that make the board appealing to any user. This board can be sold by Parallax, Terasic, or even both of them.
Terasic is official Altera Global Kit Reseller (the same for Digilent with Xilinx). The advantages and disadvantages are still the same between made by Parallax or made by Terasic/Digilentinc. Higher costs and lower user base if made by Parallax.
But Its true. Parallax is another option. Can easily jump into it, and I will be glad if they start making FPGA development boards.
Anyway, I realize the way to do P3 might be to build a generic big-FPGA board with an FPGA that is supported by Quartus Web Edition (no $3k/year cost for the tools), so that everybody can buy one and compile on it. We keep the base processor code open and current, so that you guys could compile it yourselves, tweaking it and adding anything like synchronous serial on your own, to prove things. You'd all become versed in Verilog and hardware development, and we could get things refined in parallel. I guess I'd be the final arbiter of what goes in, but I think what belongs in would be readily apparent to most all involved, without much contention. The best solutions, in my experience, are usually the simplest (like Tubular's leading-%00 idea to determine task loop size), and when they pop up, they're obvious to everyone and the arguments are over. Then, the chip we fab will be quite refined and well-rounded. That would be a first in the chip-design world.
This sounds wonderful! In addition to getting forum members to help out with things like SERDES, it will let people like me play with ideas don't stand a great chance of making it into the silicon. I'm looking forward to P3 development!
This sounds wonderful! In addition to getting forum members to help out with things like SERDES, it will let people like me play with ideas don't stand a great chance of making it into the silicon. I'm looking forward to P3 development!
The Parallax MyPropeller - a large as possible, inexpensive FPGA board, programmable via an inexpensive/free tool supported by an OBEX of verilog modules that you can stitch together to make a custom Propeller - 6 COGs, no video, extra counters, extra hub? No problem. 4 COGs, in hardware QSPI?, yup, you can do that. Simple and elegant, MyProp, how I want it, nothing wasted.
Am I the only one who hasn't been able to get the update working?
I've got the DE2-115 programmed and verified with the update, and Chip's SDRAM_Graphics6.spin file loaded into the new PNut, press F10, and I get no signal
I get three cogs lights on, then after a bit it goes back to two, so it looks like the cogs are working, but the display driver isn't.
Baggers:
A few things that may help...
F11 is the compile and download
You need to use orgh $e80 and don't fill with 0's to $E80
Rom monitor now starts at $700 not $70C
Ctl-M now compiles (was Ctl-L)
Your code must now start from $E80 (I used P2load to start my program at $1000 and filled $e80-$FFF with zeros)
Currently I am not using P2Load
pnut can also use spin2 but is not fully debugged or capable
Let us know what you have to do so that I can update the sticky
You know who I am. There are a lot of people like me. I like the idea of open P3 development and I think the idea will fly by itself, but the idea that I might dig into the architecture and add or subtract a little is hard for me to fathom. BUT if you build a big board with an FPGA on it AND also a P2, using the pins that are now dedicated to memory, I think you have a winner.
The first thing that is going to happen after the P2 is released is that people are going to complain about the memory... "it is too slow... it is too small... etc. etc. etc." The next natural thing to happen is that someone will design a CPLD to handle what he considers to be "more better" memory. The job for someone like me with a P2++ would simply be to find a design that seems to do the job for me and then license or build it. I can conceive of using what is available and building an algorithmic memory processor. But I can't conceive of doing this from within the P3. The core I would need might come from within the Parallax community or it might come from somewhere else.
With a P2 on the Big FPGA board, you are selling chips, boards and building a broader conversation.
Parallax might even be seen by the industry as a potential seed point for the growth of future sales for both FPGA and licensed designs.
It never hurts to have friends.
With a P2 on the Big FPGA board, you are selling chips, boards and building a broader conversation.
Yes, I've mentioned this before.
Right now, they could do a [FPGA+P1], and the FPGA can be smaller, (and thus cheaper) and have an Expandable P1+ COG.
Here the P1+ COG can be a balanced trade-off between P1 and P2, to keep FPGA price.size down.
It should run faster then P1, but give common Code, so simple tasks slot into P1 and highest perf go into FPGA.
Once P2 is released, they can then do FPGA+P2, and the (larger) FPGA can be 1 or more P2 COGs.
Here it gets trickier, as P2 silicon is likely to be faster than a FPGA, so the more expensive FPGA gives less gain.
We keep the base processor code open and current, so that you guys could compile it yourselves, tweaking it and adding anything like synchronous serial on your own, to prove things. You'd all become versed in Verilog and hardware development, and we could get things refined in parallel. I guess I'd be the final arbiter of what goes in, but I think what belongs in would be readily apparent to most all involved, without much contention. The best solutions, in my experience, are usually the simplest (like Tubular's leading-%00 idea to determine task loop size), and when they pop up, they're obvious to everyone and the arguments are over. Then, the chip we fab will be quite refined and well-rounded. That would be a first in the chip-design world.
Okay, I'm going out on a limb here. (what else is new?) Is there any chance you might make the RTL for P2 available in a similar manner sometime soon? Many of us have FPGA boards and the Quartus tools installed. If you're planning this for P3, why not start a pilot program for P2? I know that any community generated enhancements are not likely to be in time to make it into the P2 silicon but people could be getting up to speed with the design. Would Parallax consider this?
David,
I would imagine there are those who would be very nervouse about laying all the PII design on the table at this time even before the thing is in production.
This whole open hardware at the chip level has never been done before and may need some thinking about.
David,
I would imagine there are those who would be very nervouse about laying all the PII design on the table at this time even before the thing is in production.
This whole open hardware at the chip level has never been done before and may need some thinking about.
Well, I guess I figured that if they had decided to do this for P3 they might consider it late in the P2 development cycle as well. Either way, they're potentially giving away IP that could be used by a competitor. I would hope that we're close enough to the release of P2 that no one would be able to take the IP and get something to market before Parallax. In any case, I realize that the release of the P2 RTL is a long shot at this point. I'm just anxious to try playing with some ideas that might improve C or other compiled language performance.
Personally, I would harbor considerable worry about the CPU source code being released before a first generation chip is produced.
I would worry because there are bound to be people of means, or who simply have access to a FAB and synthesis tools who can act quickly.
Once a design is in production, proven and the IP investment is being paid for, maybe...
I would worry about fragmentation. I would really worry about others not playing nice.
Assuming there are good answers for those things, refining an open CPU process may well make sense. The one attractive element in all of this is time. With development happening in parallel, perhaps with various people owning various subsystems, a model similar to Linux could fall out of all that, rapidly growing the CPU to compete with others.
Carried to an extreme, "distributions" would manifest as system on chip type devices where the core CPU IP is kept consistent and it gets packaged with other systems to form complete solutions much like ARM is used today.
Honestly, that seems viable, given Chip can be a Linus type, able to shepard things toward some productive end.
ARM continues to exist by the licensing of the IP. Linux exists because those using the IP see the value in paying the maintainers and contributors.
I guess it depends on how much Parallax revenue is generated by sales of Propeller chips vs. its educational and hobbyist products as well as development boards. It could be that chips don't generate that much of the revenue and that Parallax might benefit from having someone else make them. Of course then you lose control and someone will come out with a chip that has some COGs, an ARM core as well as a bunch of hardware peripherals like SPI, UART, I2C, etc. That don't match the Propeller philosophy and may not be interesting to Parallax as a building block.
Sorry for two posts. I'm on a Droid and contributions to this and some other forums are difficult.
That how does Parallax continue to exist and grow discussion needs to be a frank one and it needs to be real. Lots of people, families, dreams, lives depend on that answer. Open is a great thing, but it also needs to pay off.
I'm not sure it can be had here. Maybe. In any case, I personally need to see how Parallax grows and feeds itself well before I could support such an idea. Is that possible? How? I really don't see it at this early idea stage.
I do see how a trusted distribution of IP could work, but that involves legal, and it would not be open to all, just some contributors who agree to keep it in the family.
And my concern is just basic human concern. I like everybody involved with Parallax and would hate to see it go badly despite the very best intentions, that's all.
I must say, compressing time to develop for future generations is very compelling. The next ones after P2 could jump from being microcontrollers to full on CPUs.
P2 could end up being a series of microcontrollers too, perhaps one every few years or so.
But none of it makes any real sense without some established revenue and a strong center of gravity to prevent too many variations diluting the value of it all.
There is no upside to Parallax at this time. It's tantamount to them giving away their future. Maybe after the P2 has been on the market for a year or two.
Look if some of the people want to play CPU designer, they are welcome to it. There is nothing stopping them from reverse engineering the P1 and making the changes *they want* to for their idea of a P1.
They already have all the tools they need to do this. They don't need anything from Parallax.
There is no upside to Parallax at this time. It's tantamount to them giving away their future. Maybe after the P2 has been on the market for a year or two.
Look if some of the people want to play CPU designer, they are welcome to it. There is nothing stopping them from reverse engineering the P1 and making the changes *they want* to for their idea of a P1.
They already have all the tools they need to do this. They don't need anything from Parallax.
Well, I certainly wouldn't want Parallax to do anything to jeopardize their business. I suppose waiting until P2 starts generating sigificant revenue would probably be best if they intend to go the open source route at all. I only mentioned it because Chip mentioned it for P3.
Look if some of the people want to play CPU designer, they are welcome to it. There is nothing stopping them from reverse engineering the P1 and making the changes *they want* to for their idea of a P1. They already have all the tools they need to do this. They don't need anything from Parallax.
True, and the various simulators have all the code necessary to convey the ideas needed for Verilog or even vaccum tubes (valves)
There is no upside to Parallax at this time. It's tantamount to them giving away their future. Maybe after the P2 has been on the market for a year or two.
Look if some of the people want to play CPU designer, they are welcome to it. There is nothing stopping them from reverse engineering the P1 and making the changes *they want* to for their idea of a P1.
They already have all the tools they need to do this. They don't need anything from Parallax.
I guess all of these arguments against releasing source for P2 also apply to releasing source for P3. Is everyone saying that Chip's original idea was a bad one?
I think it warrants considerable discussion before being deemed bad.
It just seems to me that it's more dangerous for Parallax to release the P3 code at the beginning of a development cycle than the P2 code near the end. Anyway, it's their choice of course. I'll be happy with whatever they think is best.
So far we have only heard this open source CPU design idea from Chip. Who may well be over worked and very tired and not thinking straight:)
Meanwhile on the business side, Ken, may go completely mad at the idea. Who knows?
As I said earlier, the common wisdom in the chip design world is to keep everything secret. "Those yellow guys are going to copy everything you know".
But, is there a possible precedent? In the software world the young Linus Torvalds put his operating system out in the open decades ago. He still has control over it.
Can Chip and Parallax do the same with the Propeller?
Is it possible that the expansion of the market due to making a CPU open and letting everyone copy it still leaves more sales for Parallax than if they kept it closed?
I think these issues might need a bit of discussion within Parallax before going wild.
Currently I am of the opinion that full release is undesirable for Parallax without a lot more discussion of the pros and cons. I would hate to see a competitor grab the open IP and start making lots of various P3s or whatever. The big chip makers have bags of money and marketing clout. While it might be good for us, I don't think it would be for Parallax.
I would rather see the IP released in encrypted blocks. We can still play adding bits and contributing to the future. At least this way Parallax retains control, but gets to open up various sections for general improvement.
What we now know, is that with the two supported FPGA platforms and locked IP, we have been able to do lots of testing and suggestions. So, in hindsight, release of the FPGA code earlier would have been better.
Unfortunately, any release at this time would surely slow the P2 release
I would rather see the IP released in encrypted blocks. We can still play adding bits and contributing to the future. At least this way Parallax retains control, but gets to open up various sections for general improvement.
I can understand why that would probably be a good idea but it would make the release far less interesting to me since I'd like to muck around with the internals of the COG.
Right now, the Propeller is not one of the major competitors in the microcontroller market. If someone is going to clone a chip for profit (which relies very heavily on volume sales), they are going to target Microchip, Atmel, Qualcomm, etc. designs.
In order for someone to clone the Propeller, it first means that they believe in the chip design/philosophy enough to take on the financial risk (synthesis and fab isn't cheap, as we are all learning). Second, such companies still wouldn't be able to call their chips "Propeller", so they would have to establish their own market presence (which is also expensive). Third, unless those companies can establish market dominance, they must still implicitly rely on the success of the original product to legitimize their own product (would you buy a Propeller clone if you didn't know what a Propeller was in the first place?).
Parallax could also charge for certification of the clones. In fact, it would be in their best interest to establish this capability, even if no clones ever get certified (would you buy a Propeller clone if you knew that it didn't get certified?). The certification effectively established Parallax as the official maintainer of the Propeller design.
Considering how critical pricing is for large-volume chip sales (pennies can add up), this approach would actually open up possibilities for Parallax and the Propeller. For instance, a third-party could produce a certified 4-COG version of the Propeller with built-in flash and fewer pins (and therefore smaller package), which would potentially be much cheaper than using the 8-COG version with external flash. This alternate chip would be much more attractive to large-volume consumers, and would result in both recognition and revenue (from the certification) for Parallax in a segment of the market that the current Propeller can't touch. It is true that some low-volume customers would also buy this chip, but I doubt enough to make it a net loss for Parallax.
Comments
The licensing issue is a bigger problem but there are most likely ways around this legally by discussions with Altera. I bet they would come to the party, perhaps even with a discount for the chips. I would be a big publicity bonus for them. Otherwise we ask Xilinx
@cluso99 and others: a big FPGA board is not simple:
- at least 6 layers (2 power, 4 signal planes)
- EPCQ256 programming device and programming circuit
- 1.1 / 2.5 / 3.3 V supply voltages
- USB blaster circuit (or external JTAG programmer necessary)
I would love the opportunity to play with a P1 /P2 /P3 COG as a module that I can interface myself to FPGA pins, or add new on-chip interface blocks or new instructions to. But that would require Chip to release a COG model as a (closed, encrypted?) module that can be included in a top level Verilog program.
Parallax has been so open about P2 development (asking users about features, accepting modifications, given information about shuttle runs and die packaging shipments, offering FPGA binaries, etc ...) that for a while I though we I was part of it. So when I said *we*, I was thinking "Parallax OR the people inside the forum" as opposed to some third company (like terasic, digilentinc, Axelsys, etc...).
The same concept when I said "we ask terasic to make one" : Chip (Parallax) can ask Terasic for a custom board to start P3 development, but also with generic features that make the board appealing to any user. This board can be sold by Parallax, Terasic, or even both of them.
Terasic is official Altera Global Kit Reseller (the same for Digilent with Xilinx). The advantages and disadvantages are still the same between made by Parallax or made by Terasic/Digilentinc. Higher costs and lower user base if made by Parallax.
But Its true. Parallax is another option. Can easily jump into it, and I will be glad if they start making FPGA development boards.
=Phil
The Parallax MyPropeller - a large as possible, inexpensive FPGA board, programmable via an inexpensive/free tool supported by an OBEX of verilog modules that you can stitch together to make a custom Propeller - 6 COGs, no video, extra counters, extra hub? No problem. 4 COGs, in hardware QSPI?, yup, you can do that. Simple and elegant, MyProp, how I want it, nothing wasted.
I've got the DE2-115 programmed and verified with the update, and Chip's SDRAM_Graphics6.spin file loaded into the new PNut, press F10, and I get no signal
I get three cogs lights on, then after a bit it goes back to two, so it looks like the cogs are working, but the display driver isn't.
Any ideas?
There is now F10 for the small load, and the chip runs at 20Mhz and can be clocked up to 80Mhz. F11 is an application load and it runs at 80Mhz.
A few things that may help...
F11 is the compile and download
You need to use orgh $e80 and don't fill with 0's to $E80
Rom monitor now starts at $700 not $70C
Ctl-M now compiles (was Ctl-L)
Your code must now start from $E80 (I used P2load to start my program at $1000 and filled $e80-$FFF with zeros)
Currently I am not using P2Load
pnut can also use spin2 but is not fully debugged or capable
Let us know what you have to do so that I can update the sticky
You know who I am. There are a lot of people like me. I like the idea of open P3 development and I think the idea will fly by itself, but the idea that I might dig into the architecture and add or subtract a little is hard for me to fathom. BUT if you build a big board with an FPGA on it AND also a P2, using the pins that are now dedicated to memory, I think you have a winner.
The first thing that is going to happen after the P2 is released is that people are going to complain about the memory... "it is too slow... it is too small... etc. etc. etc." The next natural thing to happen is that someone will design a CPLD to handle what he considers to be "more better" memory. The job for someone like me with a P2++ would simply be to find a design that seems to do the job for me and then license or build it. I can conceive of using what is available and building an algorithmic memory processor. But I can't conceive of doing this from within the P3. The core I would need might come from within the Parallax community or it might come from somewhere else.
With a P2 on the Big FPGA board, you are selling chips, boards and building a broader conversation.
Parallax might even be seen by the industry as a potential seed point for the growth of future sales for both FPGA and licensed designs.
It never hurts to have friends.
Rich
Yes, I've mentioned this before.
Right now, they could do a [FPGA+P1], and the FPGA can be smaller, (and thus cheaper) and have an Expandable P1+ COG.
Here the P1+ COG can be a balanced trade-off between P1 and P2, to keep FPGA price.size down.
It should run faster then P1, but give common Code, so simple tasks slot into P1 and highest perf go into FPGA.
Once P2 is released, they can then do FPGA+P2, and the (larger) FPGA can be 1 or more P2 COGs.
Here it gets trickier, as P2 silicon is likely to be faster than a FPGA, so the more expensive FPGA gives less gain.
I would imagine there are those who would be very nervouse about laying all the PII design on the table at this time even before the thing is in production.
This whole open hardware at the chip level has never been done before and may need some thinking about.
Personally, I would harbor considerable worry about the CPU source code being released before a first generation chip is produced.
I would worry because there are bound to be people of means, or who simply have access to a FAB and synthesis tools who can act quickly.
Once a design is in production, proven and the IP investment is being paid for, maybe...
I would worry about fragmentation. I would really worry about others not playing nice.
Assuming there are good answers for those things, refining an open CPU process may well make sense. The one attractive element in all of this is time. With development happening in parallel, perhaps with various people owning various subsystems, a model similar to Linux could fall out of all that, rapidly growing the CPU to compete with others.
Carried to an extreme, "distributions" would manifest as system on chip type devices where the core CPU IP is kept consistent and it gets packaged with other systems to form complete solutions much like ARM is used today.
Honestly, that seems viable, given Chip can be a Linus type, able to shepard things toward some productive end.
ARM continues to exist by the licensing of the IP. Linux exists because those using the IP see the value in paying the maintainers and contributors.
Parallax would continue to exist how?
That how does Parallax continue to exist and grow discussion needs to be a frank one and it needs to be real. Lots of people, families, dreams, lives depend on that answer. Open is a great thing, but it also needs to pay off.
I'm not sure it can be had here. Maybe. In any case, I personally need to see how Parallax grows and feeds itself well before I could support such an idea. Is that possible? How? I really don't see it at this early idea stage.
I do see how a trusted distribution of IP could work, but that involves legal, and it would not be open to all, just some contributors who agree to keep it in the family.
And my concern is just basic human concern. I like everybody involved with Parallax and would hate to see it go badly despite the very best intentions, that's all.
I must say, compressing time to develop for future generations is very compelling. The next ones after P2 could jump from being microcontrollers to full on CPUs.
P2 could end up being a series of microcontrollers too, perhaps one every few years or so.
But none of it makes any real sense without some established revenue and a strong center of gravity to prevent too many variations diluting the value of it all.
There is no upside to Parallax at this time. It's tantamount to them giving away their future. Maybe after the P2 has been on the market for a year or two.
Look if some of the people want to play CPU designer, they are welcome to it. There is nothing stopping them from reverse engineering the P1 and making the changes *they want* to for their idea of a P1.
They already have all the tools they need to do this. They don't need anything from Parallax.
I guess all of these arguments against releasing source for P2 also apply to releasing source for P3. Is everyone saying that Chip's original idea was a bad one?
Meanwhile on the business side, Ken, may go completely mad at the idea. Who knows?
As I said earlier, the common wisdom in the chip design world is to keep everything secret. "Those yellow guys are going to copy everything you know".
But, is there a possible precedent? In the software world the young Linus Torvalds put his operating system out in the open decades ago. He still has control over it.
Can Chip and Parallax do the same with the Propeller?
Is it possible that the expansion of the market due to making a CPU open and letting everyone copy it still leaves more sales for Parallax than if they kept it closed?
I think these issues might need a bit of discussion within Parallax before going wild.
I would rather see the IP released in encrypted blocks. We can still play adding bits and contributing to the future. At least this way Parallax retains control, but gets to open up various sections for general improvement.
What we now know, is that with the two supported FPGA platforms and locked IP, we have been able to do lots of testing and suggestions. So, in hindsight, release of the FPGA code earlier would have been better.
Unfortunately, any release at this time would surely slow the P2 release
Until then just learn how to reverse engineer what is known about the P2 and incorporate it into your ideal of what a P2 should be.
Just now my gut says don't even think about it.
In order for someone to clone the Propeller, it first means that they believe in the chip design/philosophy enough to take on the financial risk (synthesis and fab isn't cheap, as we are all learning). Second, such companies still wouldn't be able to call their chips "Propeller", so they would have to establish their own market presence (which is also expensive). Third, unless those companies can establish market dominance, they must still implicitly rely on the success of the original product to legitimize their own product (would you buy a Propeller clone if you didn't know what a Propeller was in the first place?).
Parallax could also charge for certification of the clones. In fact, it would be in their best interest to establish this capability, even if no clones ever get certified (would you buy a Propeller clone if you knew that it didn't get certified?). The certification effectively established Parallax as the official maintainer of the Propeller design.
Considering how critical pricing is for large-volume chip sales (pennies can add up), this approach would actually open up possibilities for Parallax and the Propeller. For instance, a third-party could produce a certified 4-COG version of the Propeller with built-in flash and fewer pins (and therefore smaller package), which would potentially be much cheaper than using the 8-COG version with external flash. This alternate chip would be much more attractive to large-volume consumers, and would result in both recognition and revenue (from the certification) for Parallax in a segment of the market that the current Propeller can't touch. It is true that some low-volume customers would also buy this chip, but I doubt enough to make it a net loss for Parallax.