Question on D/A implementation

ozpropdev · 2013-09-07 23:03

Hi Guys

I have a question about the DAC operation in VGA video mode.
DAC0 is configured as the H-sync signal while V-sync uses a
standalone I/O pin. Is this locked in? Can it be reconfigred
to use a standalone I/O pin like v-sync. I realise this
requires a wiring change,
This would free up 1 DAC for other uses.
If not, this leads me into my next question.

Without a DAC I could implement a D/A output using the counter module.
In Propeller 1 this was done simply by loading CTRx with "DUTY" mode
and a pin definition. In Prop2 I see there are multiple "DUTY" modes.
Which one would be the equivalent?
How do you define what I/O pin to use?

I've trawled thru all the DOCs I can find, but I could not find anything.

Have I missed a post,memo somewhere?

Any ideas
Brian

Tubular · 2013-09-08 02:32

You need the cfgpins cfgdac instruction and one or two extra lines to set up counter based output. It's very easy and it is documented in Chip's document somewhere, but there is also a thread where Ariba has some demo code. I'll see if I can find that, and/or post what I did to get it going

I don't see why you couldn't just drive the H sync directly. I also think you could just update the audio in between scan lines if that's what you're trying to do

Tubular · 2013-09-08 02:43

Here's what I do to drive two sinewave dac outputs

		cfgdac2 #%01			'ctrb siga on p2
		cfgdac3 #%01
		setctrb	#%01111			'dual sinewavemode
		setfrqb dacf			'dac frequency
		setwavb	wavb&#8203;			

dacf		long	214748			'3khz
wavb		long	%0100000000<<22 + %100000000<<9 + %111111111 'phase offst ampltd

cgracey · 2013-09-08 11:00

VGA VSYNC is always handled by a regular I/O pin, which is set/cleared in software. It is critical that HSYNC be a DAC output, though, since registration to pixel data is critical.

Question on D/A implementation

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