1. Famous last words, but IMHO there is no way that any reasonable P1 would fit into the MachX02 or X03. They have way too few LE's and I haven't even checked the internal ram sizes.
A MachXO2 would be used with a Prop1, not 'instead of', and the 8mm BGA could make a compact, useful module.
( On a MachXO2 scale, a Prop 1 is the same price as 1200LUT )
For MachXO3 there is simply too little hard info around yet, but unless the incremental logic cost of creating a P1 is less than a P1 device, you are better simply placing the P1 along side.
There may be a small opening, if the FPGA P1.5 can run a lot faster, but in FPGA land speed == $$.
Sorry haven't browsed the entire thread, but I'd add a vote for 64 I/O pins, and add support
for separate I/O voltage (1.8V upto 5V, possibly segmented in to two 32 bit groups)
I think there are a couple of branches possible here :
a) A Prop 1 module with a moderate FPGA alongside, think "Quickstart F+"
MachXO2 would fit well here. eg
LCMXO2-4000HC-4MG132C 4320 LUTS, 105 I/O, 3.3V 100: $8.52 8x8mm BGA
LCMXO2-2000HC-4TG100C 2112 LUTS, 80 I/O, 3.3V, 100: $8.13 TQFP100 - maybe too large ?
LCMXO2-1200HC-4TG100C 1280 LUTS 80 I/O 3.3V 100: $5.87
LCMXO2-640HC-4TG100C 640 LUTS, 79 I/O, 3.3V, 100: $4.72
LCMXO2-256HC-4TG100C 256 LUTS 56 I/O 3.3V 100: $3.40
b) Larger FPGA, with Prop 1.5 IP included. Users can add more FPGA code, and could expand OBEX.
The MachXO3 might fit here ?
Thinking some more about this, I think a third combination could make more sense, as it looks like a FPGA will always cost more than a Prop 1.
c) A Prop 1 module with a largish MachXO2/XO3, alongside, and a single COG optionally in the FPGA.
Here, most SW runs in the Prop 1, but the FPGA COG is (hopefully) faster and has higher MHz on counters etc, and could even directly map peripherals into Register space, so it can give a significant boost to P1 designs, (toward P2) and because only a single COG needs fit, the FPGA price impact is less.
The COG code, would be best as a P2- ie a Prop2 opcode set, but with 'fat' stuff like Maths-ops removed, or done more serially.
Comments
A MachXO2 would be used with a Prop1, not 'instead of', and the 8mm BGA could make a compact, useful module.
( On a MachXO2 scale, a Prop 1 is the same price as 1200LUT )
For MachXO3 there is simply too little hard info around yet, but unless the incremental logic cost of creating a P1 is less than a P1 device, you are better simply placing the P1 along side.
There may be a small opening, if the FPGA P1.5 can run a lot faster, but in FPGA land speed == $$.
for separate I/O voltage (1.8V upto 5V, possibly segmented in to two 32 bit groups)
Sorry this post makes little sense. It was in reply to another one which is now deleted.
Thinking some more about this, I think a third combination could make more sense, as it looks like a FPGA will always cost more than a Prop 1.
c) A Prop 1 module with a largish MachXO2/XO3, alongside, and a single COG optionally in the FPGA.
Here, most SW runs in the Prop 1, but the FPGA COG is (hopefully) faster and has higher MHz on counters etc, and could even directly map peripherals into Register space, so it can give a significant boost to P1 designs, (toward P2) and because only a single COG needs fit, the FPGA price impact is less.
The COG code, would be best as a P2- ie a Prop2 opcode set, but with 'fat' stuff like Maths-ops removed, or done more serially.
http://www.bugblat.com/products/tif/
http://www.bugblat.com/products/pif/
I think the tif one is using the 8mm BGA package, which would sit well alongside a P1.