Need a little help with Open Hardware Conference material
cgracey
Posts: 14,206
David Carrier and I are presenting a talk at the Open Hardware Conference in Boston this Friday on how the Prop2 was designed with help from members of this forum.
Do any of you have ideas for compelling talking points and/or imagery for slides? We've got to have the slides submitted tomorrow, but the talk can be thought about until the last moment.
Thanks. -Chip
Do any of you have ideas for compelling talking points and/or imagery for slides? We've got to have the slides submitted tomorrow, but the talk can be thought about until the last moment.
Thanks. -Chip
Comments
2) two high speed counters per cog
3) CORDIC
4) the P2 invaders - done in one cog with threads
5) 4 fast ADC's per cog
6) separate video/component/vga engine per cog
7) {RD|WR}QLONG 128 bit memory reads/writes
8) 1080p30 component video possible in once cog running at 3/8th speed of "real" silicon
9) 32MB SDRAM on your upcoming modules
... and much more ....
Here is a short list that I came up with, but it is not at all complete:
- texture mapping, helped by Andre LaMothe
- code protection, helped by Pedward, who even came up with PASM code to do SHA-256
- Spin2 XOR atomic PINx/DIRx operations using shadow registers, helped by Andy (Switzerland)
- multi-threading, encouraged by several, including Heater
- I know Bill Henning made lots of contributions, too.
Who made what contributions is not really important for the presentation - only that openness leads to better designs.
Basically, what highlights can you recall of forum interaction leading to Prop2 design improvements? It might be good to show a few snippets of posts which were effecting the design. Many of you can likely remember better than I, as my memory is a steel sieve when under pressure.
I believe that around this time ideas on speeding up Hub operations were also being floated.
From there, it is notable how you would pose key design discussions to the forum and consult with people qualified to help you produce optimal hardware support for key features.
There definitely needs to be some brief discussion about the "do it in software with silicon assist" and deterministic design ideologies and how the community had validated those with P1 and the impact of that on P2.
Late in the game the value of the chip was improved considerably when you and Heater had an exchange about multi threading, and you, I and a couple others discussed a monitor and how that could impact and support on chip native test, debug and development.
Call me, if you want to. I've got some time this evening to discuss. I believe this presentation is an extremely good opportunity for you and Parallax.
- chip layouts and walkthroughs by beau and chip
- admitting your errors and being able to communicate within hours/days of that temporary setback
- how to design chips (textbook reference at some point)
- even the manufacturing cost price of the prop2 at some point (!)
Off the top of my head Cluso I think suggested some pin mode decoding using weak pullups, and Sapieha had many instruction suggestions.
But... given you really need visual material right now, and since the P2 threads are large and testamant to just how open and involved everyone has been, would it be possible (web/database skills) to grab the avatar of everyone who has contributed to those massive threads and to combine it into a single slide?
I'll see if I can find it.
Found a reference:
http://forums.parallax.com/showthread.php/144199-Propeller-II-Emulation-of-the-P2-on-DE0-NANO-amp-DE2-115-FPGA-boards?p=1149377&viewfull=1#post1149377
C.W.
I'm still not sure if Atomic timer access made the cut - we are still waiting on timer details
I think the largest single jump was from multi-threading, and that was a quite-late design revision.
When doing slides, be sure to have one that shows this :
Replies: 2,286 Views: 281,664
For a device that is not released, that's some large numbers.
and include some examples of the FPGA platforms, as that allowed real code to be tested, and to some extent, removes the silicon from the critical path.
Will you have packaged (tested?) silicon to take to the conference ?
http://forums.parallax.com/showthread.php/90019-What-would-you-want-more-of-cogs-or-RAM
There was a few threads earlier on relating to open hardware, and they happened near the time that Chip said the ROM was encrypted to protect IP. Some discussion on that happened, then Chip said, "if somebody can get it, I'll publish" and Hippy did just a little while later on.
Sometime after that, the idea of open stuff really started to bubble up with lots of comments from many of us about Windows only tools, lack of an open compiler for SPIN and other things. Much of that centered on how tools change, closed vendors cause troubles, Parallax's own adventures with the PIC, the SX and some other basic things like aversion to patents and attorneys.
With P1 firmly out the door and rocking, Chip begins work on P2.
Enter that thread above: That was really the first major discussion of the chip. Many of us participated, with Chip taking input and having discussions of pros and cons.
There are some good highlights in there, such as 8 or 16 COGS and what that means for performance, and RAM sizes related to the above. Latency / HUB transfer rates and threads were all discussed in great detail.
Here's the take away from that, and the dynamic to set the stage for the years of development to follow:
Chip has some idea of where he wants the design to go. However, basic value statements features / costs / impacts aren't clear at that early stage, so he triggers discussion. Ideas range from sane to nuts and that's fine. All are heard.
Then Chip weighs what he learned, visualizes the design implications back to core silicon features that might be needed or that would support a potent cross-section of the problem space as identified by discussion above.
**Frankly, that's where the genius is.
Some time passes, Chip, along with Beau begin layout and design work.
Chip articulates some core ideas he wants to do. One of those is on-chip development. This idea was met with considerable discussion, not all of it positive. The idea fades throughout the design process as the focus ends up centered on chip features.
This cycle repeats a few times, a combination of potential design paths, costs, time, and the chip begins to take shape.
Chip all the while has been building bits and pieces on FPGA to test out the chunks that get discussed and identify core feature / function. This is demonstrated with video, and discussed with HUB I/O early on.
The need to intercommunicate across COGS is hashed out, and this one is notable, and I need to check whether or not it's in this thread, or the newer one we've got cooking on the P2 forum right now. But, that one ranged all over the place, and it's obvious Chip is struggling with simplicity. Many ideas are put out, but they are complex or too modal or too expensive in the silicon.
(cont)
In addition to the theme that "openness leads to better designs" they'll be interested in what's actually been shared/released with the Propeller 1. I think you've shared everything you can short of the whole die design though pictures have been explained and it's been browsed in UPE events, so you might want to use one slide to list out the pieces that have been published: Spin interpreter, compiler, C-GCC tool chain, SimpleIDE, etc. Might want to throw in your opinion about [absence of] patents on our chip as well as some advice about lawyers in innovation. Be aware that some people might be in the venture funding world and build intellectual property collections as part of their company's value.
Twelve minutes isn't much time. If you are both presenting then I suggest you do all of the talking as few of these people have met you before and because you speak well in front of groups. They are already familiar with David.
Dress comfortably, like if you were going to Tehama County Farmer's Meeting or a fundraising event for the school. Something like that.
- Ken
Chip appears to come to us, get ideas, thoughts, and then goes off to mull it over. In the case of the inter-cog comms, Chip eventually settles it with a simple mode of communication and masks, port D.
Sorry, this is a little out of order:
Early on, we had some discussions on bit size, SPIN RAM and a few other scaling things. It was determined that backward compatability was not a priority and that SPIN needed to have a larger memory space. That debate was notable for how far it ranged, from a possible P3, to different trade-offs between efficiency and address space.
In each major instance, once Chip has got things sorted, it was brought back for validation of sorts. Most things validated nicely, with Chip contributing his reasoning. In come cases, there is very significant disagreement and there were frequent expressions of "it's a mistake" and Chip appears confident his core design ideology that brought us P1 remains the right path and he carries most of it forward to P2, despite disagreements.
(It turns out, once we get the FPGA emulations, Chip is right about it based on what we know right now)
So there are points of conflict, but for the most part, it's a "family fight" with everybody really interested in making something great happen. That needs to be said, because it's true. Those of us who adopted P1 really do see the great pieces and so far P2 is looking to be a real firecracker...
For specific topics, where the group really doesn't have the core understanding needed to flesh out silicon, Chip seeks trusted advisers. Roy, Andre', Pedward, Bill Henning, others.
Somewhere in here, the decision to keep the ROM simple and externalize SPIN was made. The P2 would be a more traditional design in that respect, containing only what is needed for booting.
The COG gets expanded with STACK and CLUT RAM capabilities, originally needed for video, but they prove handy to close some other gaps in the P1 design as well.
Now, I think this is a process that Chip needs to speak to. I found it notable that both Chip and the group could come to know things were missing. Chip filled those gaps, and sometimes received information and or had meetings to that end.
By this time, the old thread had wound down and the newer one picked up. And somewhere about this time, Chip realizes he can't scale to the new design and meet time expectations. Synthesis begins.
We get a few presentations at the annual conferences about where the P2 design is, problems to overcome, expenses, silicon trade-offs.
Pre-release P2 information gets released to a few select members working on open GCC development tools.
One complicated discussion was code protection. Chip expresses extreme dislike for it, however group advocacy by those concerned about adoption being limited without it, make the case over objections of other forum members. Code protect is in.
The same process iterates, features discussed, details resolved, and Pedward offers his understanding of these things. Chip gets on board really interested in a scheme that works well and that has options and is water tight.
Around this time, Chip decides to provide an on-chip monitor
A chance discussion about multi-threading sees a lucid comment by Heater. Chip gets it, and turns around a hardware multi-threading modification in the course of just a handful of days. What? 11, 9? I can't remember.
[quite a bit of P2 related discussion happens on various features]
Chip publishes the boot ROM and monitor.
FPGA Emulations were released. There were some objections about this all around, Chip assures people it's difficult to reverse-engineer and that is validated by others in the community.
Testing begins!
We get basic tools Chip is using for development. These are "pre-Alpha" though quite usable, given the sparse bits of information Chip was able to provide to date.
Documentation releases also begin.
A bug gets identified. Somebody else here will identify who it is, and I think it's Bill. Chip decides to change the synthesis at considerable cost. This should be in the presentation for sure. This would have been a major gaffe solidified into the chip and expensive to fix. Caught early.
Many things decided and vetted early actually. Truth is, some design choices may have been less optimal, some features missed entirely had the process not been open. The difference between the chip we've got on the table now and the one originally envisioned is amazing.
As documentation releases continue, community begins to add resources of their own, code gets written, and advanced features tested. Video, multi-tasking, math, etc...
There is much speculation about the true capability, each being slowly validated by various early projects happening on the FPGA.
And that needs to be in the slides too! Once the FPGA is out, things begin to happen in parallel. Some people are pushing the limits of code, including a full game in one cog, while others test out and learn to use specific features. Documentation efforts, Prop GCC for P2, Chip working on SPIN 2, etc...
The effort is starting to snowball a little, with board designs and planning for real parts meshing with code, external RAM, and all kinds of other little details coming together as people are interested in, or Parallax needs / prioritizes.
SPIN 2 gets a little mini discussion using the same iteratitive process seen for the P2 design process as a whole. Some core features identified from limits / struggles people had when pushing the limits on SPIN 1 on P1.
We get inline PASM pointers to things we didn't have before, and an intrepeter designed to take best advantage of the significantly more advanced COGS.
Lots of stuff missing of course, but maybe that helps ferret out a few basic slides... I may post up some later.
The old P2 development thread(s) need to be searched for actual P2 design ideas/suggestions. I don't have time today.
BTW I like tubulars suggestion of putting together our avitars on a slide.
P2 Emulation on DE0 & DE2 FPGA Boards ("sticky") - latest info on using the DE0 & DE2 emulators is kept up-to-date by the forum users
http://forums.parallax.com/showthread.php/144199-Propeller-II-Emulation-of-the-P2-on-DE0-NANO-amp-DE2-115-FPGA-boards
The first post of this thread contains links for the latest versions of...
FPGA code & pnut.exe including Getting Started on DE0 & DE2
P2 Instruction Set including documentation by users from Chip's info
P2 Monitor Rom documentation by Doug (potatohead)
P2 Loader by David Betz
P2 Prop Terminal by Andy
Needs an update - could users please post latest updates and links to their projects/threads here so I can update the first post, tks.
Other interesting threads and projects...
P2 PAL/NTSC/Interlaced/NonInterlaced Composite/Component Drivers by Jim (baggers)
http://forums.parallax.com/newreply.php?do=postreply&t=149989
P2 HDTV Component 1980x1020p Display by Jim (baggers)
http://forums.parallax.com/showthread.php/147962-HTDV-Component-1920x1080p-Display-)
P2 Invaders in 1 Cog by Brian (opropdev) - possible to do run multiple separate copies in one P2
http://forums.parallax.com/showthread.php/149825-PROP2-Invaders-1-Cog
P2 WireWorld Computer Demo by Jim (baggers) - Game with VGA 800x600
http://forums.parallax.com/showthread.php/147457-The-WireWorld-Computer
P2 GCC - TV Demo by Jim (baggers)
http://forums.parallax.com/showthread.php/148219-Propeller-GCC-TV-Demo
P2 pnut.exe loads all128KB
http://forums.parallax.com/showthread.php/148611-New-PNUT.EXE-loads-all-128KB-of-Hub-RAM
Extensions to the compiler suggested by Chris (Sapieha) - ORGH, ORGF
P2load by David Betz - Includes additions as suggested by forum members.
http://forums.parallax.com/showthread.php/144384-p2load-A-Loader-for-the-Propeller-II
P2 SDRAM Driver by Chip
http://forums.parallax.com/showthread.php/147301-SDRAM-Driver
P2 LMM Debugger by Ray (Cluso99) - runs in same cog as user code ready for the P2 (originally based on released monitor rom code)
http://forums.parallax.com/showthread.php/146688-LMM-P2-Debugger-Uses-Serial-Tx-amp-Rx-for-debugging-single-cog-programs
P2 GCC New Release - David Betz
http://forums.parallax.com/showthread.php/146269-New-version-of-PropGCC-for-P2-posted-on-Google-Code
P2 SHx/RCx/ROx C Flag operation different in P2 by Ray (Cluso99)
http://forums.parallax.com/showthread.php/147953-Operation-of-C-flag-in-SHx-RCx-ROx-different-in-P2
P2 JMPRET/PUSHZC/POPZC Notes by Brian (ozpropdev)
http://forums.parallax.com/showthread.php/148405-JMPRET-PUSHZC-POPZC-notes
P2 PINx & DIRx and AND/ANDN/OR/XOR Behaviour - Questions by Ray (Cluso99)
http://forums.parallax.com/showthread.php/148254-Question-about-the-PINx-amp-DIRx-registers-and-instructions-AND-ANDN-OR-XOR-behaviour
P2 Unofficial Documentation Project - started by Peter Jakacki
http://forums.parallax.com/showthread.php/144432-The-unofficial-P2-documentation-project
P2 Fast Minimum-Footprint Bytecode Interpreter by Chip - from suggestion by Doug (potatohead)
http://forums.parallax.com/showthread.php/147870-Fast-minimum-footprint-bytecode-interpreter
How will the P2 be marketed -general user discussion
http://forums.parallax.com/showthread.php/147672-How-will-the-P2-be-marketed
Openness...
P2 arrives but doesn't work
http://forums.parallax.com/showthread.php/147806-Prop2-arrives-today-but-it-won-t-work
P2 SPIN2 Function Pointers by Chip - asking for suggestions/feedback
http://forums.parallax.com/showthread.php/147930-Function-Pointers-in-Spin2
P2 Die Picture
http://forums.parallax.com/showthread.php/147820-Propeller-2-die-picture
What has made openness work so spectacularly with the P2 design is that it's so skillfully woven with Chip's singular vision for how things ought to fit and work together. Without such a unifying vision, openness can lead to chaos, i.e. "design by committee." That Chip was able to keep his mind's eye focused on his vision for the P2, given all the input he was receiving, filtering, and in some cases accepting will, in large part, be what makes the P2 a successful product.
But I know that Chip is too modest and generous to point that out in his own presentation.
-Phil
Do any of you want to volunteer to make that collage of relevant users' avatars? Any other images would be welcomed, too. Can any of you take a picture of your DE0/DE2 setup, with it being attached to something, like maybe a monitor? You could place your avatar into the image, too. Maybe I can show them that with enough "openness", your own workload becomes negligible, and this could be the basis of a new economy. That might resonate well.
You are most phenomenal when you speak extemporaneously. If the rules permit, leave time for at least one question.
If you still need images you're welcome to the Smorgasboard, it's open source and unique as far as I know, and should resonate with that crowd. There is also Matanya, MacTuxLin's Propeller-powered story telling robot, introducing the smorgasboard here:-
http://www.youtube.com/watch?feature=player_embedded&v=J4V5Trf_s0w
Medium Smorgasboard image here:-
http://smorgasboard.wikispaces.com/file/view/smorg_m.jpg/320994370/smorg_m.jpg
"
What has made openness work so spectacularly with the P2 design is that it's so skillfully woven with Chip's singular vision for how things ought to fit and work together. Without such a unifying vision, openness can lead to chaos, i.e. "design by committee." That Chip was able to keep his mind's eye focused on his vision for the P2, given all the input he was receiving, filtering, and in some cases accepting will, in large part, be what makes the P2 a successful product."
Chip, this needs to be said. Be humble about it, like you always are, but it's the part of the process that really works, and that worked in our favor. Perhaps a parallel event would be Linus and how he continues to shape Linux.
http://forums.parallax.com/archive/index.php/t-106059.html
http://The unofficial P2 documentation project
Here is one example: http://forums.parallax.com/showthread.php/146621-Prop2-Texture-Mapping
If required we can use print screen and paste it into MS Windows paint to save them as png files,
http://forums.parallax.com/showthread.php/90019-What-would-you-want-more-of -cogs -or-RAM
With the question from Chip: That really is throwing a fundamental decision out to the crowd.
I'm sure I argued for more RAM instead of COGs at some point but I don't feature in that thread.
The highlight of all this for me was what happened with threads. In August 2012, very late in the design cycle when everything is pretty much set in stone, I casually suggested: Chip's classic reply was: Only a matter of days later Chip had it working, amazing!
Turns out I was not the first to make this suggestion. I just happened to make it at a crucial moment. I'm quite proud of it, It might be the most profound effect I have ever had on anything in the computing industry.
The threads are here:
http://forums.parallax.com/showthread.php/141706-Propeller-II?p=1117188&viewfull =1#post1117188
http://forums.parallax.com/showthread.php/141706-Propeller-II?p=1117193&viewfull =1#post1117193
http://forums.parallax.com/showthread.php/141706-Propeller-II?p=1122134&viewfull =1#post1122134
@Heater, yes. I thought so too. That thread is really where the core discussion kicked off.
The one with the whisker in it, is NTSC component video, interlaced. The other two are waveform captures I happened to take photos of.
potatohead, Is there a cat contributing to open hardware in there?
Many of us are very happy you said it when you did. I too was stunned to see it happen so quick!
This when all the crazy cog / hub schemes were being discussed. We all ended up settling on 8 cogs, and Chip later on went for the higher throughput HUB read / write schemes.
IMHO, we totally got to the right place, but it took a lot of discussion. On that one, it's worth noting that Chip went ahead and started asking us hard questions. Questions that made everybody think about it, and one by one, we sort of backed off on 16 COGS. Was very interesting.
Of course, we then got threads, which turned out fantastic.
And that should go into the slides.
One element of this is everybody contributes core things they know. Chip can select those and apply them to the core things he's building on. Many of us have done this, many times to great effect.