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eeprom data sheet question — Parallax Forums

eeprom data sheet question

RforbesRforbes Posts: 281
edited 2013-07-28 05:56 in Learn with BlocklyProp
Hey all :)

I'm trying to learn more about the eeprom on the quickstart and i2c in general.

On the datasheet for this eeprom http://ww1.microchip.com/downloads/en/DeviceDoc/21203Q.pdf on page 2, the parameter D7 calls out a pin capacitance of 10 pf and the notes section says Vcc=5.0v TA=25C and Fclk=1MHz.

I'm trying to figure out what the capacitance should be at 3.3 volt and 400 kHz.
Capacitive reactance is 1 / 2 pi f c but it seems like there is more to figuring this out than just just determining the reactance and then rearranging for 400 kHz.

Can you help me out a bit here?
Thanks
Robert

Comments

  • Mike GreenMike Green Posts: 23,101
    edited 2013-07-27 10:09
    The pin capacitance would be very slightly less at a lower supply voltage. Part of this capacitance is passive physical ... the capacitance of one conductor to another when run close together to each other, like between the package leads or between metalization conductors on the surface of the chip. Part of this capacitance is dynamic, consisting of reversed biased semiconductor junctions in input gates or static protection diodes. This is what would depend on operating voltage levels. I'm not sure how the capacitance would depend on the clock frequency. I suspect they specify that more to indicate the operating conditions of the chip rather than any significant dependence on it. Note that the pin capacitance is specified as a maximum. I suspect it varies quite a bit from part to part and from pin to pin. A maximum is given so that the total capacitive load of a number of I2C parts on the same bus can be estimated.
  • RforbesRforbes Posts: 281
    edited 2013-07-27 14:41
    Mike, thanks for the good explanation. I found this article http://www.edn.com/design/analog/4371297/Design-calculations-for-robust-I2C-communications and it talks about a need to reduce the size of the pullups when increasing the bus speed or when there is a lot of bus capacitance at the end of the article- but doesn't really give an explanation why. In other posts here I've read that slowing down the bus allows for longer cables, and since longer cables=more capacitance this seemed to make a little bit of sense with the reactance issue, barring any other knowledge. So, I thought perhaps the capacitive reactance at a given clock frequency was a driving force behind this.

    I'm waiting on some B82P714 i2c bus extender chips to show up in the mail and would like to experiment with long cables, varying speeds and pullup resistors so wanted to try and see which formula applies (or doesn't!.)

    Do you know of any good online calculation sites that allow you to plug in some numbers to get a good approximation of characteristics for a given bus design?
  • Mike GreenMike Green Posts: 23,101
    edited 2013-07-27 15:05
    Reducing the size of the pullups increases the amount of current available for charging the capacitance of the cable and the devices at the other end. Slowing down the bus allows more time for the capacitances to charge and discharge. It also allows switching transients to die out. Having a controlled impedance for the cable helps too and you can add matching resistors at the far end to help reduce and absorb reflections.
  • RforbesRforbes Posts: 281
    edited 2013-07-27 15:22
    Ok, it's making a little more sense to me now. By "matching resistors" at the far end, are you referring to putting pullups close to the slave node on the end of the cable? And I'm not sure what you mean by reflections?
  • Mike GreenMike Green Posts: 23,101
    edited 2013-07-27 20:20
    Any cable at the frequencies we're talking about, particularly the transition times (from low to high or high to low), we're talking about RF and transmission lines. Any such cable has a characteristic impedance and, for best power transfer to a load, the load impedance has to match the transmission line's impedance and the transmitter (whatever is generating the signal) transfers the most power to the line when its impedance is matched to the load (the transmission line and the load at the other end). If these matches are not made, some of the energy will bounce back causing reflections and these will cause noise at the receiving end and loss of power at the transmitting end.

    A matching resistor corrects a mismatch at the far end and absorbs some of the reflections caused by the mismatch. If the source and load are well matched in impedance and the cable is matched as well, there is little in the way of reflections and the noise caused by them.

    Look at discussions of transmission lines, impedance matching, and reflections.
  • RforbesRforbes Posts: 281
    edited 2013-07-28 05:56
    Ah, this is great! Thanks so much.
    Robert
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