One issue is that the PEK still does not specify using bypass caps as far as I know. Maybe it's been corrected, but I don't think so. Parallax is a great company, but one thing they should work on is updating their documents and software.
Humanoido, add bypass caps to your schematic. It's the right thing to do. Claiming that they're hidden in the power supply doesn't make sense.
It is mentioned on page 38 of the latest PEK manual.
I don't think I would fault Parallax for not showing decoupling and or filter caps in a minimal Prop schematic.
One often sees minimal circuits like that that are intended to show a concept or a use case of a device, the clutter of "housekeeping" components being left out for clarity. It is often expected that a designer will be aware of these details and take care of them.
For any writer worth reading, context and audience are of critical importance.
If Parallax is addressing engineers... bare bones conceptual schematics are fine.
If Parallax is addressing naive beginneers... be literal... include the critical components, but one doesn't have to junk up an exemplar with everything under the sun.
So what's the problem here? I suspect not being sure who is the audience.
So what's the problem here? I suspect not being sure who is the audience.
This is probably true, but even if the audience is very well defined different people will still have varying opinions on what that audience needs.
For example, some people think "simple code" means hide everything except the key lines. This is true until the point where a problem shows up and then all possible information is required to debug. The thing with programs is that there isn't much one can do to break the chip. If a bad code design practice is suggested, it usually only hurts the writer's reputation. In hardware using a bad design practice can actually break the chip and hurt the customer.
It's still not clear to me whether the root cause of pll failures is by leaving one of the VDD pins unconnected or the lack of proper bypass with both VDD pins connected. Anyone have actual experimental data?
There was some discussion of this when it was first discovered. Chip looked at the design and decided that voltage drops across the chip in the power distribution network were responsible when either one set of Vdd/Vss pins were not connected or when the bypass capacitors were missing or too far from the chip. The PLL multiplexer was the most vulnerable just because of where it lay in the power distribution network. If the chip was rearranged, some other structure would be the primary failure point. What happens is that a portion of the chip transiently is powered by Vdd/Vss less a voltage drop across the chip while some of the inputs of that portion come from another section of the chip without the voltage drop and that input voltage exceeds the limits of the transistor structures involved since they're powered via the voltage drop and they eventually fail. When the two pairs of Vdd/Vss pins are connected together and to the power source via a low impedance connection (as the chip is designed for), the voltage drop across the chip is reduced to where this problem doesn't occur.
Comments
It is mentioned on page 38 of the latest PEK manual.
http://www.parallax.com/Portals/0/Downloads/docs/prod/prop/PEKitLabs-v1.2.pdf
C.W.
For any writer worth reading, context and audience are of critical importance.
If Parallax is addressing engineers... bare bones conceptual schematics are fine.
If Parallax is addressing naive beginneers... be literal... include the critical components, but one doesn't have to junk up an exemplar with everything under the sun.
So what's the problem here? I suspect not being sure who is the audience.
This is probably true, but even if the audience is very well defined different people will still have varying opinions on what that audience needs.
For example, some people think "simple code" means hide everything except the key lines. This is true until the point where a problem shows up and then all possible information is required to debug. The thing with programs is that there isn't much one can do to break the chip. If a bad code design practice is suggested, it usually only hurts the writer's reputation. In hardware using a bad design practice can actually break the chip and hurt the customer.
It's still not clear to me whether the root cause of pll failures is by leaving one of the VDD pins unconnected or the lack of proper bypass with both VDD pins connected. Anyone have actual experimental data?