Propeller 2 Release Date ?
megaionstorm
Posts: 178
In how many months/years would the Propeller 2 be released ?
megaionstorm
Posts: 178
Comments
The 2 FPGA development boards are the DE0-Nano and DE2-115 Terasic boards. The DE0-Nanao emulates a 1 COG P2 with 32 I/O and 32KB RAM. The DE2-115 does 5 COGs, 96KB RAM. Both run at 60MHz.
Depends on several factors:
- Our cost per die of fabrication, packaging and testing. Chip provided numbers (a couple of dollars) informally at the Official Propeller Conference based on our TSMC fabrication plans. This particular foundry has a much higher startup cost for shuttle and mask set, but a lower unit cost. We are presently looking at alternatives which might increase our unit cost per die, but have a lower shuttle/mask cost. Our recent submittal had a poly layer error, so we are evaluating an alternative for the next foundry run. Bottom line: we don't know what our fabrication costs will be at this stage.
- Desired Rate of Return Depending on our projected volume, and your price, how quickly we expect to make a return on our investment. This isn't the most useful variable to consider in pricing the Propeller 2, however.
- Target application volumes High-volume customers can drive the costs down for low-volume customers. If we obtain some large designs with Propeller 2 then our costs decrease, along with yours.
- Customer's volume Parallax has a large number of customers who want a small number of chips, and a much smaller number of customers who want a large volume of chips. Chances are the price curve will be fairly steep until 1000 units (higher price at low volume, much less above 1K units).
I imagine a low-volume price would be between $15-20, and production pricing around $10, but it's too early to say. Our current priority is to get a working Propeller 2, and then hopefully we can have a meaningful discussion with our customers about price. We'll be very open with you when this time comes.However, Propeller II is a complicated microcontroller, totaling in 20 - 30s million transistors so it actually took a lot of attention just to do it right - what just happened also have proved something more important; presistence. From Chip and Beau, we also have learned much about chip-making, and how difficulty it is.
So, we might have better luck in early Autumn due to TSMC's run schedules and test / burn-in to determine the final price-out based on yields. I am waiting also, having learned all about chip-making myself.
Yet, Propeller still have enough punches (due to eight COGs, one CPU core for each COGs), and we only have got that far with them.
???
However, the CPU cores in both microcontrollers are electrically arranged so they are dealt with in a round-robin (if you have dealt with SPARC CPU, it's somewhat similar but different).
The CPU cores in both microcontrollers are obviously different - the first being very, very simple (think 32-bit version of 6502), while propeller II being multi-threaded again similar to SPARC so you can stuff four - eight threads in a particular COG which makes Propeller II even more powerful.
Why "COG"? You guess it, it's like clockworks - going around like an actual clock (if this analogy sucks, I apologize).
A COG is basically a 32 bit CPU, or "core" as they might say elsewhere.
To be clear, all 8 COGs can operate at full speed at the same time. And they all have direct access to all the I/O pins, at full speed.
When Dr Mario says "arranged so they are dealt with in a round-robin" that only comes into effect when COGs are accessing the main 32Kb of RAM (or ROM and a couple of other operations). In that case they have to "wait their turn" to access main memory.
This is all made clear by some nice diagrams in the Propeller manual.
KC_Rob - yup, that's doable, and pjv's own RTOS kernel come to mind - multi-threading on P1 is intentionally done to keep the active COGs busy, so it can keep tracks of events as defined by Systick generated by counters. I actually like this kernel, pretty simple and elegant if you think about it.
where can we learn more about the kernel you mentioned? it is here:
http://www.parallax.com/PropRTOS/tabid/852/Default.aspx
Call it the V8, since it's got 8 cylinders and a distributor!
Then you can start a naming convention like Maxtor did with their hard drives. They would put pictures of muscle cars on the board, a GTO, etc.
It doesn't seem so goofy when it's a diverse metaphor basis.
Pedward, that's a good analogy.
Is this correct? So it it 8x faster than the P1? (2x clock speed, 4x (less) clocks per instruction?)
If so, will (counter) control of I/Os be 1/4 of clock (SDeR) or 1.5625ns resolution?
I think the counters work at the system clock rate, so the I/Os work with a 6.25ns resolution. Video is different since it works at multiples of the system clock. You'll have to actually look at the P2 documentation since I'm going from memory that may be stale or incorrect.
New instructions allow you to read the lower and upper 32 bits