When doing our presentation on the Prop2 on Saturday afternoon, Beau noticed something that wasn't right *snip*
I assume this means the whole synthesized logic block is dead, or just the edges? Could you still test things like the fuses by hacking in with the FIB machine?
I assume this means the whole synthesized logic block is dead, or just the edges? Could you still test things like the fuses by hacking in with the FIB machine?
Lawson
There are too many connections to FIB to bother trying anything. We just need to re-fabricate it. The whole main logic block is dead.
Just an idea... You could still use the bad chips to test your board production with 0.4 mm lead spaced chips.
(trying to make lemonade here )
Or, if you know you have that under control, give them to others to try.
I ruined a few chips trying to solder it by hand. Did get it right on the third try though...
Anyway, bad chips can still be good for solder testing.
Just an idea... You could still use the bad chips to test your board production with 0.4 mm lead spaced chips.
(trying to make lemonade here )
Or, if you know you have that under control, give them to others to try.
I ruined a few chips trying to solder it by hand. Did get it right on the third try though...
Anyway, bad chips can still be good for solder testing.
That's an interesting idea, Ray. Even though they're useless, this could be quite the expensive learn-to-solder program with 199 chips for $60,000. That's $300/P2 chip. Don't wipe that big soldering iron across the leads so quickly!
That's an interesting idea, Ray. Even though they're useless, this could be quite the expensive learn-to-solder program with 199 chips for $60,000. That's $300/P2 chip. Don't wipe that big soldering iron across the leads so quickly!
Maybe they'd be best used as "booby" prizes. I.e. mount 'em on a snarky pcb and hand them out to vendors/customers who make simple yet hard to find mistakes with spectacular consequences?
It wasn't a design flaw, the best I can figure is it's like laying out a PCB. It's analogous to having a short between traces because the flood fill didn't use the right settings.
Yep, it's basically a short. Some cells overlapped. Beau can explain how, but that's the gist of it. The overlap is in the main logic block and it's significant enough to prevent operation.
Just an idea... You could still use the bad chips to test your board production with 0.4 mm lead spaced chips.
(trying to make lemonade here )
One hopes even a DRC failure can still be used for some verification testing.
Depends on how many places the poly-bridges are 'fatal', and what defaults around the peripheral.
Such density-fillers, are less likely to be in dense areas, so may affect only some channels/operations.
I guess even ESD testing would give useful info, and it is less painful zapping to limits, a chip that is not-much-usable.
I know code crackers often sniff the Icc patterns, so it may be possible to check something like ROM boot, at least to the point where it waits on real pin change. Default PLL should also be check-able.
Very sorry to hear this. What a bummer. Is it a total waste?
Best of luck on the next set and hopefully it will not take too many more iterations for a completed prop 2.
To minimize any speculation there might be, the errors are all located within the core logic.
What I saw when zooming in during the presentation was a DRC violation formed due to FILL-cell overlapping a standard cell. (See Image #1 & Image #2 for an example) This however is not an isolated incident, there are several locations throughout the core that this scenario plays out. To further elaborate on the two images, Image #1 is a representation of the layers that were turned on during the presentation (Poly-Green ; and Diffusion-Brown). A transistor is formed when poly crosses diffusion. Poly is used for the Gate and where the poly 'cuts' the diffusion, the Source and Drain of the transistor are formed. The error in this image is located at about the center of the image. The minimum DRC rule for POLY to POLY spacing is 0.25um, the minimum width of the POLY is 0.18um which defines the 180nm process. During the presentation I saw this and my mental red-flag was seeing that the POLY to POLY spacing was less than the actual width of the POLY. In this example view, the error creates a rail to rail short between VDD and GND, but this is not necessarily the case with the other violations. In image #2 Additional layers Metal #1(blue) and contact (White) have been turned on. The contact is simply a via that allows Metal #1 to connect to Poly or Metal #1 to connect to diffusion. In this particular view Power and Ground are strapped causing a short.
The error was immediately obvious to me, but before I said anything I needed to further investigate the issue to be sure. As far as blaming anyone or the tool, I should have caught this early on, and largely I blame myself, but as Chip mentioned in the presentation there are several details that are involved during closure of the design and unfortunately we missed a big one. The core logic should have already had density fill for Poly and Diffusion when we received the work on it, but unfortunately it did not. The former being the case I would not be writing this update. The core logic that we received only had metal density applied to metal layers 1 to 6 but skipped poly and diffusion which are also valid metal layers. In an attempt to meet metal density rules the existing FILL cells were modified on our end with proper fill percentages. These percentage values are suggested by the manufacturer and are designed to help increase yield, but in this case we completely killed the yield.
Because the errors are all within the core, our tool is not capable of running an LVS to check for any shorts within the core unless we can convert the Verilog into a SPICE file, something our current layout editing tool-set can't perform.
We can do a DRC, but because of the size and number of connections within the core, the DRC will need to be a "windowed" DRC where we specify smaller sections at a time to aim the tool at.
Some would argue that as art proceeds from the mind;
and as the artist can be found in the art,
it will not be long before the inner working of the chip will measure to
the creative charge of its creators.
Good things take time, and are worth the wait.
I'm looking forward to your success!
In this example view, the error creates a rail to rail short between VDD and GND, but this is not necessarily the case with the other violations.
So what is the resistance of the unwanted link, vs the supply rail bus-bars ?
Can you inject enough voltage to test logic, even if the supply droop/skews mean you cannot clock at any speed ?
There will be upper limits (something just over 2V?) and lower limits (something near 1V), but that's a reasonable skew to allow low speed functional testing ?
We can do a DRC, but because of the size and number of connections within the core, the DRC will need to be a "windowed" DRC where we specify smaller sections at a time to aim the tool at.
If you can split out the information by-layer (and the new added fills should be easy to split, and relatively small), then you could run some across-layer checking tools. I've mentioned above that some Gerber tools do this, and Gerber is a very simple, dumb format.
If you can keep at least one data-set small, then checking can be sped up significantly.
But a request for all of our customers. Let's not use this as an opportunity to encourage additional design improvements to Fozzy Bear. These changes could open up more synthesis, I/O frame changes and lots of expense. The cost of design changes and running chips is so much more than the $60,000 shuttle runs mentioned on Saturday - it includes synthesis consultants, salaries, administrative costs, quick-turn packaging, mask sets, etc.
Hello Ken,
Some time ago I tried to find IC design and shuttle prices. It was difficult for me to get the information as I don't work in this area. I heard MOSIS prices was one time open to public, but not now anymore. But this is what I found:
As they have minimum order of 40 samples, have you ever considered any other foundry with lower MOQ to make prototypes?
I am also interested in knowing Mask prices. I have found mask prices for over >1 micron sizes, but there is no public information for masks in submicron sizes.
Also interested in layout software prices. Please, can you point me to some places to find this information. Direct contact with corporate emails is like a knocking a wall.
USB support, Ethernet, really advanced graphics controls are examples of things I hope not to see encouraged at this time. All we want to do is get these metal layers straight and go back to the foundry.
Sorry, I fell guilty of doing that recently, I will stop until you open the Prop 3 feature request ;-)
Apparently, once you choose a foundry you don't switch: each foundry is sufficiently unique where changes have prohibitively high costs.
And that's the bottom line. They all have their own design rules and some level of compatibility. There's much more in an agreement beyond shuttle runs. Production quantities and mask sets are priced at the same time which could really change how shuttle run pricing is viewed.
I'm thinking about buying a DE2-115 now... Was holding off when it looked like chips were only a few weeks away...
But with them 8 weeks out, it's more justifiable for me...
When doing our presentation on the Prop2 on Saturday afternoon, Beau noticed something that wasn't right as he zoomed into the synthesized logic layout. It turns out that some poly density fill we added to the blank standard cells was conflicting with actual circuitry. We didn't realize that the 'fill' cells were sometimes placed in non-integral positions, overlapping onto adjacent circuitry. So, these chip's coming in today are not going to work. We will only be able to do a power-up test on the I/O ports, which doesn't tell us much. We must resubmit the design database without the fill patterns and get this fabricated again on the next shuttle run. So, it will be another 8 weeks, or so, before we might have functional Prop2 chips.
Beau said when he saw that poly conflict, he got a really sick feeling, hoping it was maybe just a mistake in the database he was displaying. I remember his mood changing during the presentation, but didn't know what to make of it. He verified afterwards that it was, indeed, a problem. It didn't occur to either of us that there would have been anything to see there, as that block was delivered to us already checked. Our attempt to meet minimum poly density requirements backfired, unfortunately.
I am really sorry to hear this, I know how hard Parallax has worked to get the P2 on the market. This would be a good time to work on the different drivers.
To minimize any speculation there might be, the errors are all located within the core logic. (*snip*)
I can only imagine how gut-wrenching this was to discover. But I have to thank you (in a perverse way) for the mistake. Having never done the sort of work you and Chip have been doing, I am finding all of this (both good and bad parts) to be extremely educational. Your openness, candidness, and willingness to put in the extra effort to show the exact nature of the failure is very refreshing (and valuable).
Comments
We'll just keep them secret, for now.
I assume this means the whole synthesized logic block is dead, or just the edges? Could you still test things like the fuses by hacking in with the FIB machine?
Lawson
ROFL!!
All kidding aside. I'm sure that you'll get the problem solved quickly and this will end up being a minor delay.
There are too many connections to FIB to bother trying anything. We just need to re-fabricate it. The whole main logic block is dead.
Bruce
(trying to make lemonade here
Or, if you know you have that under control, give them to others to try.
I ruined a few chips trying to solder it by hand. Did get it right on the third try though...
Anyway, bad chips can still be good for solder testing.
That's an interesting idea, Ray. Even though they're useless, this could be quite the expensive learn-to-solder program with 199 chips for $60,000. That's $300/P2 chip. Don't wipe that big soldering iron across the leads so quickly!
(ducks and hides)
Maybe they'd be best used as "booby" prizes. I.e. mount 'em on a snarky pcb and hand them out to vendors/customers who make simple yet hard to find mistakes with spectacular consequences?
Lawson
One hopes even a DRC failure can still be used for some verification testing.
Depends on how many places the poly-bridges are 'fatal', and what defaults around the peripheral.
Such density-fillers, are less likely to be in dense areas, so may affect only some channels/operations.
I guess even ESD testing would give useful info, and it is less painful zapping to limits, a chip that is not-much-usable.
I know code crackers often sniff the Icc patterns, so it may be possible to check something like ROM boot, at least to the point where it waits on real pin change. Default PLL should also be check-able.
Best of luck on the next set and hopefully it will not take too many more iterations for a completed prop 2.
"Did he died?"
What I saw when zooming in during the presentation was a DRC violation formed due to FILL-cell overlapping a standard cell. (See Image #1 & Image #2 for an example) This however is not an isolated incident, there are several locations throughout the core that this scenario plays out. To further elaborate on the two images, Image #1 is a representation of the layers that were turned on during the presentation (Poly-Green ; and Diffusion-Brown). A transistor is formed when poly crosses diffusion. Poly is used for the Gate and where the poly 'cuts' the diffusion, the Source and Drain of the transistor are formed. The error in this image is located at about the center of the image. The minimum DRC rule for POLY to POLY spacing is 0.25um, the minimum width of the POLY is 0.18um which defines the 180nm process. During the presentation I saw this and my mental red-flag was seeing that the POLY to POLY spacing was less than the actual width of the POLY. In this example view, the error creates a rail to rail short between VDD and GND, but this is not necessarily the case with the other violations. In image #2 Additional layers Metal #1(blue) and contact (White) have been turned on. The contact is simply a via that allows Metal #1 to connect to Poly or Metal #1 to connect to diffusion. In this particular view Power and Ground are strapped causing a short.
The error was immediately obvious to me, but before I said anything I needed to further investigate the issue to be sure. As far as blaming anyone or the tool, I should have caught this early on, and largely I blame myself, but as Chip mentioned in the presentation there are several details that are involved during closure of the design and unfortunately we missed a big one. The core logic should have already had density fill for Poly and Diffusion when we received the work on it, but unfortunately it did not. The former being the case I would not be writing this update. The core logic that we received only had metal density applied to metal layers 1 to 6 but skipped poly and diffusion which are also valid metal layers. In an attempt to meet metal density rules the existing FILL cells were modified on our end with proper fill percentages. These percentage values are suggested by the manufacturer and are designed to help increase yield, but in this case we completely killed the yield.
Because the errors are all within the core, our tool is not capable of running an LVS to check for any shorts within the core unless we can convert the Verilog into a SPICE file, something our current layout editing tool-set can't perform.
We can do a DRC, but because of the size and number of connections within the core, the DRC will need to be a "windowed" DRC where we specify smaller sections at a time to aim the tool at.
and as the artist can be found in the art,
it will not be long before the inner working of the chip will measure to
the creative charge of its creators.
Good things take time, and are worth the wait.
I'm looking forward to your success!
But keep your chins high - you are really doing an amazing job on what is only a shoestring budget compared to the "other" chip manufacturers.
And we have the DE0 & DE2 to continue on with - and this is really amazing.
As for those chips, as has been suggested, get Chip to sign them and perhaps auction them?
Wasn't intended to be.
We all make mistakes. I can imagine the gut-punch feeling he must have felt. Have felt it myself, numerous times.
So what is the resistance of the unwanted link, vs the supply rail bus-bars ?
Can you inject enough voltage to test logic, even if the supply droop/skews mean you cannot clock at any speed ?
There will be upper limits (something just over 2V?) and lower limits (something near 1V), but that's a reasonable skew to allow low speed functional testing ?
If you can split out the information by-layer (and the new added fills should be easy to split, and relatively small), then you could run some across-layer checking tools. I've mentioned above that some Gerber tools do this, and Gerber is a very simple, dumb format.
If you can keep at least one data-set small, then checking can be sped up significantly.
Hello Ken,
Some time ago I tried to find IC design and shuttle prices. It was difficult for me to get the information as I don't work in this area. I heard MOSIS prices was one time open to public, but not now anymore. But this is what I found:
Source: CMP France, 2012:
AustriaMicrosystems 0.18um 1290 Euros/mm2 MOQ: 25 samples
TowerJazz 0.18um 1400 Euros/mm2 MOQ: 25 samples
Source: Europractice MPW General, 2012
AustriaMicrosystems 0.18um 1200 Euros/mm2 MOQ: 40 samples
UMC L180 Logic GII 0.18um 640 Euros/mm2 MOQ: 45 samples Min Size: 5x5 (16000 Euros/block)
Source: Europractice MPW mini@sic
UMC L180 1P6M 0.18um 1148 Euros/mm2 MOQ: 20 samples
TSMC 0.18um 1431 Euros/mm2 MOQ: 40 samples
How good are TSMC dealing with small runs?.
As they have minimum order of 40 samples, have you ever considered any other foundry with lower MOQ to make prototypes?
I am also interested in knowing Mask prices. I have found mask prices for over >1 micron sizes, but there is no public information for masks in submicron sizes.
Also interested in layout software prices. Please, can you point me to some places to find this information. Direct contact with corporate emails is like a knocking a wall.
Sorry, I fell guilty of doing that recently, I will stop until you open the Prop 3 feature request ;-)
I hope great success in the next run.
Apparently, once you choose a foundry you don't switch: each foundry is sufficiently unique where changes have prohibitively high costs.
And that's the bottom line. They all have their own design rules and some level of compatibility. There's much more in an agreement beyond shuttle runs. Production quantities and mask sets are priced at the same time which could really change how shuttle run pricing is viewed.
But with them 8 weeks out, it's more justifiable for me...
Are the Parallax DE2 boards still available?
Rich
I am really sorry to hear this, I know how hard Parallax has worked to get the P2 on the market. This would be a good time to work on the different drivers.
Almost.
I can only imagine how gut-wrenching this was to discover. But I have to thank you (in a perverse way) for the mistake. Having never done the sort of work you and Chip have been doing, I am finding all of this (both good and bad parts) to be extremely educational. Your openness, candidness, and willingness to put in the extra effort to show the exact nature of the failure is very refreshing (and valuable).