How will the P2 be marketed?
David Betz
Posts: 14,511
We've had lots of cool demos posted here that show off the graphics capabilities of the P2. They are truely awesome! Is that the target market Parallax is shooting for? The P2 has lots of nice hardware to accelerate video and graphics. Is that where Parallax expects the P2 market to be? Is that what marketing will focus on when trying to sell the chip to people outside of the forums?
Comments
I have on my desk selection of ARM boards that drive HDMI TV's and monitors, play games using OpenGL, play videos at as good a qualty as you can get from a TV playing DVD's have stero sound and so on. Given that these offer superb graphics at a price down in the pocket money bracket I don't see the Prop making inroads there. Especially since they also come with networking, USB, etc etc thrown in.
Now I did say, "At least not by themselves". What the Prop has that they do not is:
a) Buckets of I/O
b) Analog I/O if you want
c) Great real-time, real world event handling.
d) Great simplicity when doing c)
As someone, somewhere here as already said, it's that combination of graphics features and real world interfacing that needs exploiting for Prop II "killer applications"
I could see a lot of scope for instrumentation, experiment control, control systems etc where graphics on a small screen, a few buttons and great real world connectivity would be just brilliant.
I really do the P2 as potentially a neat indie game platform because it creates a universe that isn't so unbounded, unlike the Android ecosphere. If you have limits, people will try to push against those limits and create some really amazing things.
A second gen Hydra, perhaps the HydraX or DeusHydra, would be a really useful tool for game programmers to cut their teeth on and build up the important skills that are needed for upper echelon gaming.
We still don't have half the I/O drivers that the P2 will bring to reality. Soft USB, Ethernet, all manner of interconnected things.
I could see this chip being the killer chip for some appliance device that gets put in many homes.
I also think SDR is a very real possibility with this chip generating the IF signals and controlling an external oscillator.
Rather if anything it will be niche applications (mostly smaller scale): instrumentation and control, I/O & real-time intensive, specialized data interfaces, and so forth. In general, things for which an FPGA or a muti-core or PRU-supplemented ARM would be overkill. The P2 will have, or should have, at least in theory, advantages in ease-of-use and reduced development time. ARM processors are not so easy to program on bare-metal systems, and not every application requires or benefits from a full-blown Linux (or some other OS). FPGAs are likewise unsuited for many projects, just from a complexity standpoint if no other reason. Something will fill those gaps; if done right, that something could be the P2.
...and a nuts number of sound channels.
T'was Chip who mentioned the real world interaction and graphics, and I would add sound.
There is a style element in play. My kids and their peers listen to a lot of music that has effects and often coarse ones.
Say one had two 16 bit channels through whatever needs to be added on. Then say it offered something nuts like 8 or 16 more traceable, bendable, controllable channels. The mains get mixed in with the rest, but the effect channels are piped in all over the place! Put some in the floor, walls overhead, etc... In the right hands that would be a lot of fun!
Now I'm rather unsure about the gaming aspect. There are just so many options out there I've lost count. Now as a super Uze-Box for hackers to pound on, and that is easy to code as a old Atari ST or Amiga, I can see a future for it. But GCC will need a very good graphics and audio library to make it accessible for mere mortals. Maybe a subset of OpenGL, Cairo?
I'd agree - for pumping large amount of memory, P2 is not optimal, but many users are buying 'smart pins' and the P2 can slot into many IO tasks, and it also sits well between Micros and FPGAs.
FPGAs have tended to run-away from the base-line users as they chase the higher priced cutting edge, and the Trailing edge FPGAs are still not that cheap. (features have gone up, rather than prices come down..)
A P2 could allow many users to drop a size or three in FPGA and that is worth a lot of money.
Or it can be treated as a Analog-FPGA.
There is plenty of scope in the 'nimble and smart IO' space, that is even expanding, as the Linux Boards rumble onwards.
As the 'main iron' gets more layers of SW, there is more room for 'coal face' parts to be smarter and faster.
The ADCs are sigma delta, 4 per COG, using the counter channels. They are successive approximation, just like the P1 soft ADCs, and you can determine the resolution as a slider between time and bits. If you want fast deterministic low-bit ADCs, you can, if you want slow but high-bit ADCs, you can have that too.
The max value is 32bits AFAIK, so the theoretical max is 1 / 2^32 * Vio, or 7.6834112e-10 ( 0.000000000076834112 volts).
Is there more info on this yet ?
Can the sampling clock be adjusted independently in hardware, wihout slowing anything else down ?
- allowing use of external integrators, and switched references for better S/N ?
On the Prop2, the integrators are within the pin circuitry and clocked there. There is a mode for external feedback loop, but it is still clocked within the pin circuitry, so you won't get those circuitous delays that you have on Prop1.
Well, one aspect of this is graphics happens to be a great way to get to know PASM and how the data can flow within the chip. When we get real chips, using the powerful I/O pins will become more of a focus. And we've got C and PASM to work with right now.
(I too am looking forward to your "get started example David, and was going to ask about it on the C discussion we had recently.)
Personally, I'm starting to feel good about PASM. Still lots to learn, but a lot of things come fairly easily now. Graphics also matches up fairly well here too as simple things that are very useful later on can get packed into a few COGS with few worries.
The more robust input is going to be awesome! When real chips get out there, people are going to do a lot of interesting things. So much power at the pins now! IMHO, that should prove attractive and very useful, and there are a lot of them. We talked about an I/O extender. Hang a P2 off of a lot of systems with a simple comms protocol, and a lot can be done! Getting some graphics, good quality even off of one single pin is a nice bonus. I'm looking forward to that part of things myself.
Thinking about games for a moment... You know, having the analog I/O options really opens up a lot of doors! Complex, multi-axis input schemes won't be difficult, and will be more than responsive enough. By and large, we've settled on moderate latency controllers. Couple that with display and compute latencies (buffers, math, etc...), and things can approach 50-100ms! One thing a P2 can do easily is deliver spot on, frame accurate interaction, and it can do so on a very wide variety of control schemes. Heck, do it with multiple displays and suddenly the potential for a really immersive experience is possible. There is that nexus again between real world events, DSP and PC type graphics. A lot can be done with what we are seeing right now and I think that will be compelling if it's exploited in the right ways. It is those same attributes that made me think of the live performance device. It counts there.
In any case, thanks Chip! I read your comments on the other thread, and agree with them. I sure hope it's possible to secure the business needed to keep it all going. This whole thing is kind of special in that way.
I guess the inbuilt R/C & parasitic L's mean you do not know the noise floor until the part is done ? (or did the test silicon include this?)
For the external paths option, as the chip-part is only digital, it should be possible to get some noise floor numbers on the FPGA emulation ?
In external mode, can the clock be changed without change of COG speed ?
It is clear from this thread and the other ([thread]147500[/thread]) thread that RPi and BBB are a significant attraction and that P2 cannot compete in that arena. So it seems that one of the best things that the P2 could do is show how easily you could use it with those devices. Forget getting USB or Ethernet working out-of-the box! Instead, make sure that it's ridiculously easy to interface the P2 from an embedded host system (RPi, BBB, and a couple of the Arduino models immediately come to mind). For instance, put together a Linux device driver and a P2 "shield" that allows non-hardware people to get up and going quickly (plug-and-play?). The shield could potentially come with an eeprom preloaded with a solid set of soft peripherals, which could be conditionally loaded via device driver IOCTL calls (or whatever). And if it turns out that someone needs a peripheral that's not included, just load it up through the same device driver (possibly even storing it to the eeprom for later retrieval). Along with that, emphasize the following (not exhaustive) features:
- Implement the peripherals that meet the project's needs instead of trying to figure out if the main board has those capabilities (i.e. pick the host for the rapid development and familiarity, not whether it has enough ADCs, PWM, etc.)
- Move from one embedded platform to another (e.g. from RPi to BBB, from BBB to whatever comes along next) without having to redo any of the peripheral support
- Excellent re-usability (Done with that one project, but need to do different peripherals for another project? No Problem!)
- Excellent adaptability (Equipment interface obsolescence? No problem!)
If the P2 can get mind share in this way, it is inevitable that some of the users will start to ask the question "can I do what I need with just the P2?" (This, of course, is where having native support for USB and Ethernet would be important.)In fact, this might even be an ideal approach to attracting P2 users:
- Make it easy to interface from an embedded host system.
- For those that want to commercialize/simplify/etc, show how they can potentially get rid of the host system altogether!
Just getting a chunk of the market for step one would make P2 successful. A market share based on step two would be a bonus.Seairth, I think you are right about all this. That's where the market is right now, and it would probably be a good strategy to pitch the Prop2 as a helper chip, which would lead people into using it for more, later on.
What I would suggest having on any piggyback or breakout board, is 5V (or more?) IO on maybe 24 pins ?
Many new Single Chip alternatives are wide-vcc, and the Single Board PC blocks, tend to lack 5V IO., so this gives you an important distinction.
@Seairth: Love the idea of PC/RPi/BBB libraries to easily use a Prop2 as a real-world IO peripheral. If this all works through the programming interface, the driver could load a new program as needed (i.e. no EEPROM or flash required) and it should work with any prototyping board.
Lawson
I mean a low cost hobby work horse with an standardized and easily understood addressable expansion bus and a way to program directly on the machine and that will autoload a program file stored on a sd card. or something like that.
I agree with a lot of what you wrote... especially the last part
Actually both USB and Ethernet are great ways of connecting to RPI's et al.
Some people are interested in this. Maybe a separate thread would help determine how much interest there really is?