Any soldering iron tip friendly CPLDs available?
CuriousOne
Posts: 931
Hello. For some tasks, I need to integrate several logic elements into one compact case. Lattice has nice solutions, but simple ones are all BGA or DFN. The complex ones are TQFP or other, more solderable packages, but they are way too large both in terms of features and price. All I want is say 10 NOR, 10 NAND gates in one case, but in compact package with legs protrunding at sides, say SOT-23 or SOIC-8. Are they available?
Comments
The smallest Altera CPLD is the EPM7032B, available in PLCC44 and TQFP44.
I'm not sure what you mean by 10 NOR and SO-8, as they seem mutually exclusive, but if you want small PLDs, then look at
ATF16V8BQL / ATF16V8CZ / ATF22V10 / ATF22LV10 / ATF750
Available in PLCC20/24 TSOP20/24 and SO20W/24W - and DIP as well.
and there is also this, not quite as easy to solder, but it is very small
SLG46400 Programmable Mixed Signal Array 1.8V - 5.5V TDFN-12
http://www.silego.com/products/greenpak2.html
@CuriousOne
http://www.seeedstudio.com/depot/index.php?main_page=advanced_search_result&search_in_description=0&keyword=cpld&x=26&y=11 These are fairly cheap, you can find cool runner boards on ebay for even less but as far as I can tell they do not break out all the pins! The cool runner can be programmed with a bus pirate or a diy solution via parallel/serial cable I believe and of course using xilinx cables. I would recommend a bus pirate, on top of the awesome debugging and testing capabilities they have for the hobbyist, they can program AVR's PICs and CPLDs, even more once you buy one, you can then sample the pic from microchip in DIP format and build your own bus pirates using the one you bought as a PCI programmer. In reality though, if you are just looking for a DIP style programmable logic chip, I would stick with the list jmg provided, and research GAL circuits on google. As you can tell getting started with them is a bit confusing.
The Software flow is the same, just change Device to ATF750C, and compile in CUPL.
The ATF750 is roughly 2 x 22V10, with one x10 buried, and one x10 brought to pins.
It also has .T/,D ff, and more clock choices.
You do need a programmer that understands the ATF750C, and that is more of an issue than the tools.
Plenty ~ $100 support the 22V10, but the ATF750 is less common, and bumps the programmer price.
At that stage, you could look at the ATF1502ASL - cheaper than the ATF750CL, and JTAG ISP.
The ATFxx series SPLDs use a high voltage ( 12V region) Vpp, and there are more pins need wiggling than SPI, and I think some signatures need reading, to select pulse widths, but there is nothing a small uC could not manage.
The HW gets more complex, if you want to include Vector Testing, which is a good idea.
So you can see why universal programmers tend to be required.
20 NOR gates can go well in SOIC-8. Say I need to have output signal only when pulses on all 5 inputs arrived in specific order. All gates will be used, while having 5 inputs and 1 output.
You can make DFN easier, if you extend the fingers on a default footprint. Not as nice as gull wing, but tolerable.
PLDs can do state-engines easily, but they do need a clock for that.
They deploy best in areas where uC simply are not fast enough, or lack a feature.
eg a 16V8 can be used to add quadrature counting in HW, to a Prop, which has No QuadIn, and Up only counting.
The PLD takes the QuadIn, and outputs two clocks, which drive two counters. CW increments one counter, and CCW increments the other
The difference is your location.
If your logic is slow enough to poll, then a small uC can be better.
Something like the Z51F0410HCX comes in a SSOP10 (SO8 size, 1mm pitch) and is $1.07 100+, and costs $29.95 to kick off.
You get wide supply, of 1.8-5.5V, 12b ADC, EEPROM, Osc, and In circuit debug.
It's hard to find a 12bADC for $1.07, so the small micro is almost free....
a) 20 pin SPLD like ATF16V8BQL, where you would use 5 of the 8 macrocells. (each eqn latch point is a macrocell)
PLD code in Boolean Equation entry, is written almost as drawn. Uses 62.5% of SPLD macrocells.
b) In a small uC like Z51F0411, (10 pins) this has a some Boolean opcodes, so you can again code almost as written.
Loop time would be under 2us in a typical core. Uses < 1% of Chip resource.
; 8051 ASM Rst EQU P1.0 ; Map IO to pins Ip1 EQU P1.1 Ip2 EQU P1.2 Nout EQU P1.3 bseg at 00 ; Map latch nodes to buried pins, or Boolean memory. N1: dbit 1 N2: dbit 1 N3: dbit 1 N4: dbit 1 cseg at 0000h ;Reset vector Loop: ; N1 MOV C,N2 ORL C,Rst CPL C MOV N1,C ; N2 MOV C,N4 ORL C,Ip1 CPL C MOV N3,C ;N4;N3 MOV C,N4 ORL C,Rst CPL C MOV N3,C ;N4 MOV C,IP2 ANL C,N1 ORL C,N3 CPL C MOV N4,C ;OP MOV C,N1 ANL C,N3 MOV Nout,C SJMP Loop end ; Code Memory : 38 bytes = 0.92% used, Bit memory 4/128, Data Memory : none, SFR : noneand to complete the Boolean logic language examples, here is Pascal version.
// 8051 Pascal/Modula-2 VAR Rst : BOOLEAN absolute P1.0; Ip1 : BOOLEAN absolute P1.1; Ip2 : BOOLEAN absolute P1.2; Nout : BOOLEAN absolute P1.3; N1, N2, N3, N4 : BOOLEAN; // use 1 bit of memory, total is half a byte BEGIN REPEAT N1 := NOT (Rst OR N2); N2 := NOT (Ip1 OR N1); N3 := NOT (Rst OR N4); N4 := NOT (N3 OR (Ip2 AND N1)); Nout := N1 AND N3; UNTIL FALSE; END.The compiler may not be quite as compact as the ASM above, but it is close, and easier to maintain.