Specs on time for RESET to pull high if BOEn = VSS?

ags

I have looked at the datasheet and manual, but not found any specific specification for the timing of the RESET pin as a weak output when BOEn is tied to VSS. IOW, upon power up, with the RESET pin floating, at some point VDD reaches a threshold and causes the bootup procedure to begin. Also, with BOEn low, RESET becomes a weak output, pulled high by a 5k resistor to VDD. The question is how long is RESET low after power is applied? I plan to use this as a way to force reset on other devices in my project without "spending" a Prop I/O pin. Thanks.

Tracy Allen

Here is a PM from Parallax on this issue:
The reset signal comes in via a Schmitt trigger and goes to an asynchronous reset input on a flip-flop which traps the pulse and holds a 50ms release timer in reset. The pulse probably only needs to be 1 or 2 nanoseconds to register properly. At any rate, any low on the RESn pin gets stretched into a low-for-duration-plus-50ms pulse. After RESn goes high, the internal reset stays low for another ~50ms.

I believe you are asking about the stretching out to 50ms after RESn goes high. The reset pin is never floating when BOE is tied to Vss. It either has a 5k pullup to Vdd, or a 5k pulldown to Vss. You have to take that 5k into consideration in your scheme.

ags

Thank you for the reply. That's not quite the question I intended to ask. I'm deep into the details of the power-up timing.

Let's start with the Block Diagram, Figure 1-2 on page 20 of the Propeller Manual, v1.2. It clearly shows the 50ms reset delay you discussed above. It also shows a 10ms power up detector. Now if you look at "Boot Up Procedure"on page 18, it specifies a 100ms power-up delay. Is one of these wrong (10ms or 100ms), or are they describing different things?

I'm concerned about this because what I'm trying to understand is the timing of the signal on the RESET pin, if there is no external device driving it, during the power-up procedure. Specifically (all cases with BOEn tied low):

At the instant of power-up (VDD first applied, t0) RESET really is floating. Eventually, at some time t? RESET will be pulled high through a 5k resistor. How long is that time? I understand that the internal reset signal is extended 50ms. If BOEn was tied high, it would remain floating (an input). With BOEn tied low, what triggers the switching in of the 5k pull-up to bring RESET high?

Your response is the first indication I've had that there is also a 5k pull-down resistor, which implies that RESET can also be pulled low (weak output). When does that happen? This is the other side of the question above. How long after startup (t0) will RESET actively be pulled low rather than float? Is it pulled low for the duration of the internal reset signal (which is always >= 50ms)? Is it pulled low for the 100ms (or 10ms - which is why clarification on the power-up detector above is important) power-up detect + 50ms reset delay?

Finally, if a soft reset is executed (REBOOT instruction) is the RESET pin pulled low as well?

I hope this doesn't seem overly nit-picky; I'm trying to understand exactly how this works, and appreciate any further information you can share. Thanks.

Tracy Allen

This is the sort of question you'd best answer yourself by experiment, with an oscilloscope and probes. I agree it is somewhat ambiguous. The Prop Data sheet does not even mention the power-up delay as a separate interval.

My understanding is that the 5k resistor is attached to the output of the reset flip flop, so, if BOE=Vss, that same resistor is tied solidly either low or high, never floating except through an instant of transition. The same resistor is either pullup or pulldown, and that is why they call it "weak". My guess is that having BOE=Vss enables the reset flip flop output to the 5k resistor. That is just my guess though. Also it would be my guess that software reset does the same. If it is important for what you want to do, again, best investigate it for yourself. (and report back here!)