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Quadrature Encoder Counting — Parallax Forums

Quadrature Encoder Counting

MicksterMickster Posts: 2,698
edited 2013-04-06 18:54 in Propeller 2
I am quite excited about this capability. In theory, what will be the maximum possible frequency in terms of quadrature counts per second?

Regards,

Mickster

Comments

  • AribaAriba Posts: 2,690
    edited 2013-04-05 08:33
    We have no detailed description of this counter modes yet.
    But I guess it is 1/2 or 1/4 of the clock frequency (you need two clocks to detect a change on a pin and then you sample the other pin to decide if it is up or down).
    So I would say it is at 40..80 MHz for the real chip, and 15..30 MHz for the FPGA emulator.

    Andy
  • MicksterMickster Posts: 2,698
    edited 2013-04-05 08:45
    That would be spectacular!!!!


    Thank you.


    Mickster
  • pedwardpedward Posts: 1,642
    edited 2013-04-05 11:26
    Commercial encoders are only rated for 12,000 rpm or 1Mhz, whichever is lower, so you've got plenty of headroom. Methinks your enthusiasm may be misplaced.
  • MicksterMickster Posts: 2,698
    edited 2013-04-05 11:57
    pedward wrote: »
    Commercial encoders are only rated for 12,000 rpm or 1Mhz, whichever is lower, so you've got plenty of headroom. Methinks your enthusiasm may be misplaced.

    I have many Emerson-Control Techniques servo motors running at >6000 RPM with 4096 line encoders (16,384 quad counts/rev). My current motion controller, the Galil DMC4183 can handle frequencies to 15MHz.

    Regards,

    Mickster
  • jmgjmg Posts: 15,175
    edited 2013-04-05 14:34
    Ariba wrote: »
    We have no detailed description of this counter modes yet.
    But I guess it is 1/2 or 1/4 of the clock frequency (you need two clocks to detect a change on a pin and then you sample the other pin to decide if it is up or down).
    So I would say it is at 40..80 MHz for the real chip, and 15..30 MHz for the FPGA emulator.

    Chip must be real close by now, to finishing the Counter docs ;)

    With care, you can design to approach one clock per state, but then you need to allow margins for skew, as you have to ensure you do manage to sample at least once.
    Sometimes quad counters employ noise filtering majority-vote style, and trade off some MHz, for spike protection.

    Will be interesting to see what Speed/filtering options the Prop2 has & if it can do 2 QuadCtrs / COG.
  • MicksterMickster Posts: 2,698
    edited 2013-04-06 06:27
    Most industrial encoders provide complementary outputs (Ch A+, Ch A-, Ch B+, Ch B-, I+, I-) and typically interface to the counters via 422 line receivers for noise suppression purposes.
    & if it can do 2 QuadCtrs / COG.

    Now THAT would be incredible!

    Regards,

    Mickster
  • jmgjmg Posts: 15,175
    edited 2013-04-06 18:54
    Mickster wrote: »
    Most industrial encoders provide complementary outputs (Ch A+, Ch A-, Ch B+, Ch B-, I+, I-) and typically interface to the counters via 422 line receivers for noise suppression purposes.

    Which reminds me, I'm not sure Chip ever mentioned HW support for Index Pulses ?

    Mickster wrote: »
    if it can do 2 QuadCtrs / COG.
    Now THAT would be incredible!
    My guess would be 2 QuadsCtrs/Cog, as it makes sense to make the counters the same.
    Once Up/Down is working, it is not much logic to add Quadrature.
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