Quadrature Encoder Counting
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I am quite excited about this capability. In theory, what will be the maximum possible frequency in terms of quadrature counts per second?
Regards,
Mickster
Regards,
Mickster
Comments
But I guess it is 1/2 or 1/4 of the clock frequency (you need two clocks to detect a change on a pin and then you sample the other pin to decide if it is up or down).
So I would say it is at 40..80 MHz for the real chip, and 15..30 MHz for the FPGA emulator.
Andy
Thank you.
Mickster
I have many Emerson-Control Techniques servo motors running at >6000 RPM with 4096 line encoders (16,384 quad counts/rev). My current motion controller, the Galil DMC4183 can handle frequencies to 15MHz.
Regards,
Mickster
Chip must be real close by now, to finishing the Counter docs
With care, you can design to approach one clock per state, but then you need to allow margins for skew, as you have to ensure you do manage to sample at least once.
Sometimes quad counters employ noise filtering majority-vote style, and trade off some MHz, for spike protection.
Will be interesting to see what Speed/filtering options the Prop2 has & if it can do 2 QuadCtrs / COG.
Now THAT would be incredible!
Regards,
Mickster
Which reminds me, I'm not sure Chip ever mentioned HW support for Index Pulses ?
My guess would be 2 QuadsCtrs/Cog, as it makes sense to make the counters the same.
Once Up/Down is working, it is not much logic to add Quadrature.