23LC1024 driver

Dr_Acula · 2013-04-03 03:43

I'm doing some experiments with the 23LC1024 128k sram chip. I'm starting with a generic driver for the 23K256. I think this larger chip is just a bigger chip but it isn't working so maybe the driver is different?

The .cfg file is

# centimanes.cfg
    clkfreq: 80000000
    clkmode: XTAL1+PLL16X
    baudrate: 115200
    rxpin: 31
    txpin: 30
    cache-driver: spi_sram_cache.dat
    cache-size: 8K
    cache-param1: 0x05070601 # 0xooiiccpp - oo=mosi ii=miso cc=sck pp=cs-protocol
    cache-param2: 0x04000000 # 0xssxxxxxx - ss=cs
    load-target: ram

and the c file is the generic hello world

#include <stdio.h>
#include <propeller.h>

int main(void)
{
    int n = 1;
    while(1) {
        waitcnt(CLKFREQ/10+CNT);
        printf("Hello World %d\n", n);
        n++;
    }
    return 0;
}

and this works with the 23K256 chip but not with the new 23LC1024 chip. There is a reference within this file to spi_sram_cache.dat and I'm wondering if this references the driver code.

Is this .dat file the correct file for the chip parameters, and if so, are they different to the 23K256 by any chance?

Has anyone tried this new larger chip? http://ww1.microchip.com/downloads/en/DeviceDoc/25142A.pdf

Many thanks in advance.

David Betz · 2013-04-03 03:58

Dr_Acula wrote: »
I'm doing some experiments with the 23LC1024 128k sram chip. I'm starting with a generic driver for the 23K256. I think this larger chip is just a bigger chip but it isn't working so maybe the driver is different?

The .cfg file is
# centimanes.cfg
    clkfreq: 80000000
    clkmode: XTAL1+PLL16X
    baudrate: 115200
    rxpin: 31
    txpin: 30
    cache-driver: spi_sram_cache.dat
    cache-size: 8K
    cache-param1: 0x05070601 # 0xooiiccpp - oo=mosi ii=miso cc=sck pp=cs-protocol
    cache-param2: 0x04000000 # 0xssxxxxxx - ss=cs
    load-target: ram
and the c file is the generic hello world
#include <stdio.h>
#include <propeller.h>

int main(void)
{
    int n = 1;
    while(1) {
        waitcnt(CLKFREQ/10+CNT);
        printf("Hello World %d\n", n);
        n++;
    }
    return 0;
}
and this works with the 23K256 chip but not with the new 23LC1024 chip. There is a reference within this file to spi_sram_cache.dat and I'm wondering if this references the driver code.

Is this .dat file the correct file for the chip parameters, and if so, are they different to the 23K256 by any chance?

Has anyone tried this new larger chip? http://ww1.microchip.com/downloads/en/DeviceDoc/25142A.pdf

Many thanks in advance.

I haven't looked at the datasheet for the 23LC1024 so I can't say if the commands are compatible with the smaller chip but it shouldn't be too hard to get the sram driver to work with it. In fact, I guess I should put this on the top of my list since you, Rayman, and David Carrier are all using this chip and David Carrier is giving away two of his boards so there may be two more users wanting a driver soon. I have one of Rayman's boards so I should be able to use that for testing.

Yes, spi_sram_cache.dat is the cache driver.

David Betz · 2013-04-03 14:26

Dr_Acula wrote: »
I'm doing some experiments with the 23LC1024 128k sram chip. I'm starting with a generic driver for the 23K256. I think this larger chip is just a bigger chip but it isn't working so maybe the driver is different?

The .cfg file is
# centimanes.cfg
    clkfreq: 80000000
    clkmode: XTAL1+PLL16X
    baudrate: 115200
    rxpin: 31
    txpin: 30
    cache-driver: spi_sram_cache.dat
    cache-size: 8K
    cache-param1: 0x05070601 # 0xooiiccpp - oo=mosi ii=miso cc=sck pp=cs-protocol
    cache-param2: 0x04000000 # 0xssxxxxxx - ss=cs
    load-target: ram
and the c file is the generic hello world
#include <stdio.h>
#include <propeller.h>

int main(void)
{
    int n = 1;
    while(1) {
        waitcnt(CLKFREQ/10+CNT);
        printf("Hello World %d\n", n);
        n++;
    }
    return 0;
}
and this works with the 23K256 chip but not with the new 23LC1024 chip. There is a reference within this file to spi_sram_cache.dat and I'm wondering if this references the driver code.

Is this .dat file the correct file for the chip parameters, and if so, are they different to the 23K256 by any chance?

Has anyone tried this new larger chip? http://ww1.microchip.com/downloads/en/DeviceDoc/25142A.pdf

Many thanks in advance.

David Betz · 2013-04-03 14:28

I just looked at the datasheet for the 23LC1024 and it looks like the main difference between this chip and the smaller SRAM is that it uses a 24 bit address. That's probably why the old cache driver didn't work. I think I can pretty easily get it to use the 23LC1024 in single bit SPI mode by making a minor change to the old driver. It will take me a bit more work to get it to work in 4 bit mode. I will probably try this later tonight.

Dr_Acula · 2013-04-03 20:26

Brilliant - thanks for finding the reason. If you can get it working that would be great.

(I don't need the 4 bit mode).

Thanks++ in advance.

David Betz · 2013-04-04 05:47

Dr_Acula wrote: »

Brilliant - thanks for finding the reason. If you can get it working that would be great.

(I don't need the 4 bit mode).

Thanks++ in advance.

I got the single bit cache driver to work with the 23LC1024 chip but I seem to be having trouble with my new n-way cache code. I'm going to fix that before I move on to using the 4 bit mode of the chip. That should be pretty easy once the n-way cache bug is fixed. Then the next step will be to make use of both the flash chip and the SRAM chip at the same time. This will let me run xmm-split code on Rayman's RamPage2 board using half of the chips. After that works, I need to do the same thing but using the full 8 bit wide data path that RamPage2 supports. At that point I should be able to support either RamPage or David Carrier's new module. This same code can be used on the DNA board if you plug a 23LC1024 chip into the extra DIP8 socket Martin has provided on his board.

Dr_Acula · 2013-04-04 05:58

Thanks for all the work on this problem!. Is the single bit cache driver ready for release by any chance?

David Betz · 2013-04-04 06:03

Dr_Acula wrote: »

Thanks for all the work on this problem!. Is the single bit cache driver ready for release by any chance?

Unfortunately, the single bit driver that is currently working is really my n-way driver hacked to use only one of the ways. It's not really ready for prime time. I'll try to get it fixed soon though.

Dr_Acula · 2013-04-04 06:22

No problem, happy to wait

David Betz · 2013-04-04 07:26

Okay, I have a single bit driver working for this chip. Let me know what pins you're using and I'll post a copy of the driver and a cfg file that will work with your setup.

David Betz · 2013-04-04 09:31

Dr_Acula wrote: »

I'm doing some experiments with the 23LC1024 128k sram chip. I'm starting with a generic driver for the 23K256. I think this larger chip is just a bigger chip but it isn't working so maybe the driver is different?

It is differently mostly in that it uses a 24 bit address rather than 16 bit. Try the attached cache driver and let me know if it works for you.

spi_sram24_cache.zip

What are you doing with the /HOLD pin? Do you have it pulled high? That will be required to use single bit SPI mode.

Thanks,
David

David Betz · 2013-04-04 18:57

Okay, I now have the 4 bit driver working as well as the 1 bit one using a 4 way cache. Unfortunately, the 4 bit driver isn't that much faster than the 1 bit driver. Of course, this is very straight forward code with no fancy counter tricks. I'm sure one of the PASM wizards here could make both drivers run a lot faster.

Dr_Acula · 2013-04-04 20:11

Thanks David. Looking forward to testing this when I get home. In that zip file are some spin files - anywhere in particular that these need to go or are they just source files? I'll need to check the schematic re the hold pin but I'm 99% certain this is high.

Dr_Acula · 2013-04-04 23:39

Woot! It works.

One minor error in the files in post #11 - the last line in the .cfg file was left out "load-target: ram"

I have added this back in and attached is the corrected file. This is running on pins 4,5,6,7 and it should be fairly easy to work out from the .cfg file how to change to other pins.

David Betz · 2013-04-05 03:33

Dr_Acula wrote: »

Woot! It works.

One minor error in the files in post #11 - the last line in the .cfg file was left out "load-target: ram"

I have added this back in and attached is the corrected file. This is running on pins 4,5,6,7 and it should be fairly easy to work out from the .cfg file how to change to other pins.

That line is not needed. It works fine without it for me. Also, I used the original cfg file that you posted. I thought that had the correct pins for your board. Sorry if I was mistaken.

Dr_Acula · 2013-04-05 06:13

Brilliant work David. Thanks so much for getting this done so quickly.

The 23LC1024 128k chip really is much better than the 32k one because it can fit any spin program.

I know there are flash ram solutions, but as heater pointed out in another thread, he thinks the zicog might be next to be translated from spin. And one thing the zicog needs is a way of emulating 64k of Z80 ram, and for that you need proper ram, not flash ram, as there are lots of reads and writes. So this little 23LC1024 chip driver is going to be very handy.

Thanks again!

David Betz · 2013-04-05 06:45

Dr_Acula wrote: »

Brilliant work David. Thanks so much for getting this done so quickly.

The 23LC1024 128k chip really is much better than the 32k one because it can fit any spin program.

I know there are flash ram solutions, but as heater pointed out in another thread, he thinks the zicog might be next to be translated from spin. And one thing the zicog needs is a way of emulating 64k of Z80 ram, and for that you need proper ram, not flash ram, as there are lots of reads and writes. So this little 23LC1024 chip driver is going to be very handy.

Thanks again!

I'm glad you're finding it useful. What memory model are you using for your code? xmmc or xmm-single?

Tor · 2013-04-05 07:30

Dr_Acula wrote: »

And one thing the zicog needs is a way of emulating 64k of Z80 ram, and for that you need proper ram, not flash ram, as there are lots of reads and writes. So this little 23LC1024 chip driver is going to be very handy.

Z80/zigoc is one big reason I bought a couple of 23LC1024 chips a while back, for the day when I get some time between my hands again!

-Tor

Dr_Acula · 2013-04-05 16:21

I'm glad you're finding it useful. What memory model are you using for your code? xmmc or xmm-single?

xmmc. Is that the right one?

@Tor, I posted some thoughts on a Z80 emulation running in C on this thread http://forums.parallax.com/showthread.php/147205-Translating-the-Spin-Obex-to-C There are some cool things we can do in C that ought to make it run much faster than the Spin/Pasm emulation.

Don M · 2013-04-05 17:23

All this talk about this chip.... I ordered 3 today as samples from Microchip. Look forward to playing with them some time.

David Betz · 2013-04-05 19:49

Dr_Acula wrote: »

xmmc. Is that the right one?

xmmc is the one that puts code in external memory and data in hub memory. If that's what you're using, then you *do* need that "load-target: ram" line that I said before was unnecessary. Normally xmmc code is loaded at 0x30000000 which is usually flash memory. the "load-target: ram" tells the loader that it should load to ram rather than flash.

yeti · 2014-05-16 09:43

I just ordered some 23lc1024s.
Is all I'll need to get startet with them in the current propgcc tree (I compile from mercurial repository)?
"Default" pins for the RAM still are 4..7?

23LC1024 driver

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