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local (stack and result) alignment? — Parallax Forums

local (stack and result) alignment?

agsags Posts: 386
edited 2013-03-31 19:18 in Propeller 1
I realize that all locals (created on the stack in SPIN) and the result (return value from a method) are long-sized. Are they also long-aligned?

I'm wondering if it is guaranteed safe to pass the address of a local/result symbol to a cog through the par register. I understand the 2 LSBits of par are zeroed, in effect forcing long aligned addressing.

BTW, since a cog can address byte-aligned hub RAM, why was this done? Any why is the MSW of par zeroed? (Or are they? is the PASM entry point location stored in the high word?)

One more: is there a shadow register for par? Not sure how I could use it, other than similar to the
mov cnt,cnt
add cnt,advance
waitcnt cnt,next
pattern. Maybe for two interleaved wait states?

Comments

  • kuronekokuroneko Posts: 3,623
    edited 2013-03-31 16:27
    All stack variables (result/parameters/locals) are long aligned (they are longs after all). They can be passed to a PASM cog but you have to make sure they stay alive for the time it takes to process any data from them (once you leave the method the stack is potentially re-used). IOW if you wait until the PASM cog has placed a value into result then you're fine ([post=1136990]example[/post]).

    par is extracted from the coginit parameter register. Since the other 18bit are used for cogid and code address you only get 14bit payload. Period. And yes, there is a shadow[par].
  • agsags Posts: 386
    edited 2013-03-31 16:41
    Yes, of course you are right. I wait for a signal that the PASM code is through with the hub locations before returning from the SPIN method.

    I forgot about the cogid. That was the missing piece. So par uses 15 bits for PASM code memory location (don't need the MSB since it must be in RAM, which is only 32k address space), 14 bits for hub memory location for passing values (mailbox), and 3 bits for cogid.

    Now I call that frugal bit utilization... :-)
  • kuronekokuroneko Posts: 3,623
    edited 2013-03-31 17:07
    Actually it's a 14bit par value (long aligned), 14bit code address (long aligned) and 4bit cogid (4th bit indicates any available cog, i.e. cognew). As for not needing the MSB, how would you execute code from ROM (SPIN interpreter, boot code)?
  • agsags Posts: 386
    edited 2013-03-31 19:18
    Magic? :innocent:
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