Jitter in VGA output from DE0-nano?

pedward

I ran Bill's VGA demo on the newly received DE0-nano (Thanks Chip!) and noticed some significant noise/jitter in the generated output. I'm hoping these are just artifacts of imprecise timing and my particular LCD monitor (Dell 2007FP).

Has anyone else observed such jitter?

potatohead

I just ran it on an CRT monitor and copied the monitor ROM to the display screen on the DE2. There is a little bit of jitter. Not what you are seeing though that might just be the LCD clock circuit magnifying what is there. Here's a photo:

On a side note, I don't think I've compared the two technologies like that up close. Kind of cool to see.

Bill Henning

I noticed it as well, and it is also visible on the "color bars" demos.

At this point, my best guess is that it is due to the errors in the pixel dot clock due to the phase accumulation errors. If that is the case, the higher clock speed of the real silicon should help (assuming the PLL for video will run faster as well)

jmg

What does a scope say ?
Also remember that often a FPGA 'PLL' is often not analog, but a tapped delay line implementation, but the taps are sub-ns
Does the jitter change personality if you warm or cool the FPGA ?

potatohead

Mine is currently being stored or I would tell you. Curious about that myself. (House project + dust = stow the scope and other goodies for a time)

I did run some really high resolution pixels on a monochrome NTSC "amber screen" display. (720 pixels in safe area) They appeared more stable than the VGA ones are. Of course, those are different and lower frequencies....

Personally, I'm wondering if there isn't more variance in the NANO.