SETBC, SETBNC, SETBZ, SETBNZ instructions

pedward

I was looking at the P2 docs and saw these instructions. I wonder why they exist?

SETBC d.1
MUXC d, #1

SETBNC d.5
MUXNC d, #32

SETBZ d.1
MUXZ d, #1

SETBNZ d.5
MUXNZ d, #32

These instructions could actually be generated by the assembler transparently by using the more powerful MUX masks.

Ariba

This works for bits 0..8 but for higher bits you need a bitmask in a long for the MUX instructions.

Andy