SDRAM caching - what's best?

Igor_Rast

Flying around somewhere in dreamland , when I noticed a 1GB SRam from a laptop on my desk .

Geee . Wonder if that could be fixed to the propeller. ??
Sure is going to be handy helping out with the lcd im experimenting with

datasheet of a single mem

pedward

That's DDR2 memory, which is 2 generations ahead of what Chip is using. Chip is using what they call SDR SDRAM, 16Mx16 for a total of 32Megabytes.

jazzed

IIRC the main problem with using DDR appears to be the switching speed of signals at 1.8V (slow) -vs- 3.3V (fast). I never understood the logic of that though. SDR works with 3.3V. DDR doesn't.

pedward

I think he said "big" transistors switch slow at low voltages, and the I/O is comprised of basically 300nm transistors, which would switch too slow at 1.8v.

Igor_Rast

Thanks for trowing me out of my dream

Roy Eltham

DDR (1), runs one 2.3-2.7v, 2.5v spec +/- 0.2v. It's DDR2 that is 1.8v.

I wonder if the P2 I/O pins would switch fast enough at 2.5v or so? Of course, you need to read the data twice per clock (rise and fall edges), and the slowest DDR modules are 100Mhz clock, so it's beyond the capabilities of the stock clocked P2 to read that fast.

pedward

More importantly, the instruction that does the transfer only does SDR.

Although, you could probably use DDR and just waste half the capacity and bandwidth...

Rayman

How would we generate the clock signal for this XFR mode with SDRAM? Seems like you want it at 2X the system clock and maybe a little out of phase, right?

Ariba

From the pinout.txt in the Emulator-Files-Zip:

* All SDRAM input and output signals are delayed by 1 clock
  in order to emulate the SDRAM pin mode on the Prop2 chip.
  The SDRAM CLK pin (not shown) is driven directly  by the
  FPGA with the Propeller II system clock (inverted to meet
  SDRAM waveform requirements).

pedward

I would assume DDR commands are done at single clock rate and transfers are done at double rate. You wouldn't gain anything by doubling the clock rate because the data is transferred on different edges.

The fastest true clock rate for SDRAM is only 166Mhz I think, I don't think they go faster than that yet.

Rayman

ok, the sdram posted here is sdr, so i guess we need it at just 1X prop freq (not sure what i was thinking...)
Still,how do we output that?

Ariba

My understanding of Chips description is that the FPGA always outputs the clock to the SDRAM.
An if I look with a scope at the clk pin of the RAM then I see a signal.

Andy