Parallax Prop2 Module - Questions, Facts and Speculation
JRetSapDoog
Posts: 954
Although actual silicon and boards are still a ways off, perhaps we could use this thread to gather questions, facts and speculation regarding the Prop2 Module that Parallax will produce. In part, this thread is motivated by the following words from Chip in Bill Henning's HDTV P2 forum thread:
"Once we get a good driver for the on-board SDRAM written, you'll be able to do much better resolution and color depth. The standard Prop2 module that we will make will have an 8MB flash and a 32MB SDRAM, so big memory will be somewhat of a standard. On the DE0/DE2 boards, the SDRAM is connected the same way it will be on the Prop2 module."
Just a few seed questions to kick things off:
Are any diagrams available showing dimensions and the proposed component layout?
What chips are being considered for the 32MB SDRAM part that will provide the "big memory"?
Will the 32MB SDRAM chip be mounted on the reverse side as in the DE0 Nano or on the "main" side?
What resources will be required to drive the SDRAM in terms of total pins, cogs and so on?
Will an SD/uSD socket be present (IIRC, a rather minimal/flexible board is envisioned w/o such a socket)?
What kind of connectivity or connecivity options will be provided for off-module connections (headers, etc.)?
What other questions and speculation do you have? What other info is available from other threads?
Recently, Chip stated that one of the next things on his agenda (if not "the" next thing) is to write a driver for the SDRAM on the FPGA boards, so hopefully it's not too early to start musing about Parallax's Prop2 Module. Although many applications won't require SDRAM, Parallax's plan to produce a module with SDRAM included is exciting and could provide the basis for many powerful projects. Of course, forum members and others will produce their own modules and Parallax is encouraging that, but having a standard module available from the P2's creator will really kickstart a lot of creativity.
Crosslink for More Prop 2 Module Details: http://forums.parallax.com/showthread.php/147772-What-type-of-boards-will-be-available
"Once we get a good driver for the on-board SDRAM written, you'll be able to do much better resolution and color depth. The standard Prop2 module that we will make will have an 8MB flash and a 32MB SDRAM, so big memory will be somewhat of a standard. On the DE0/DE2 boards, the SDRAM is connected the same way it will be on the Prop2 module."
Just a few seed questions to kick things off:
Are any diagrams available showing dimensions and the proposed component layout?
What chips are being considered for the 32MB SDRAM part that will provide the "big memory"?
Will the 32MB SDRAM chip be mounted on the reverse side as in the DE0 Nano or on the "main" side?
What resources will be required to drive the SDRAM in terms of total pins, cogs and so on?
Will an SD/uSD socket be present (IIRC, a rather minimal/flexible board is envisioned w/o such a socket)?
What kind of connectivity or connecivity options will be provided for off-module connections (headers, etc.)?
What other questions and speculation do you have? What other info is available from other threads?
Recently, Chip stated that one of the next things on his agenda (if not "the" next thing) is to write a driver for the SDRAM on the FPGA boards, so hopefully it's not too early to start musing about Parallax's Prop2 Module. Although many applications won't require SDRAM, Parallax's plan to produce a module with SDRAM included is exciting and could provide the basis for many powerful projects. Of course, forum members and others will produce their own modules and Parallax is encouraging that, but having a standard module available from the P2's creator will really kickstart a lot of creativity.
Crosslink for More Prop 2 Module Details: http://forums.parallax.com/showthread.php/147772-What-type-of-boards-will-be-available
Comments
Prop2_Module.pdf
The DE0 and DE2 Prop2 emulation boards and the Parallax Prop2 module have the same schematic from pins 48 on up. Whatever SDRAM driver is written for one will work for the others.
We aren't sure yet what to do about the connector that the module will need. Jeff here has found that we can get PCI connectors for $0.27 each, which is really inexpensive, but means the module would be longer than it otherwise would need to be, to accommodate the edge connector. We were also thinking about putting solder pads out to the edges on the backside so that the whole board could be treated as a lead-less surface-mount component.
From the rough layout, it looks like the module (perhaps not including the connector) will be quite small, on the order of 1.25"x1.00" or so. Update: I wouldn't be surprised if it's bigger than that but still fairly compact.
Apparently, the components are all on the top side of the module. Wonder if it's a 2-layer, 2-layer + GND/PWR planes, or 4-layer design.
It appears that we just need to supply 3V3 and the module will generate 1V8 with that Micrel synchronous buck regulator onboard.
The module's connector exposes the first 47 Prop 2 pins (P0-P46). The Winbond SDRAM uses most/39 of the remaining 45 pins (Update: See Roy's Post #21).
The possibility of solder pads out to the edges on the backside is intriguing. Would that require "oven" soldering? Or would some edge-soldering technique be possible? Or what about some kind of castellated edges (though maybe too expensive)? Anyway, the connectivity sounds like a tough decision (for the future) to make.
About the SDRAM driver, I'm wondering if driving it will take a whole cog. Perhaps there will be space leftover from driving (reading/writing and any needed refresh) to add other/related code.
Could someone comment about the advantages (or necessity) of the inductors distributed around the Prop 2? In combination with the caps, do they provide for better filtering and/or will they somehow help the A/D (or D/A) response and so on?
Looks like Parallax has a great module in the works. Thanks again, Chip, for providing those details.
Thanks for posting the PDF - it looks really good. I like the minimalistic design with only a big flash and an sdram.
Looks like P47 will be the SDRAM clock, correct?
Regarding the connector, what about 0.1" holes on either side? Then it would be possible to plug the board into breadboards.
As I recall, Chip mentioned that 16 bits made a perfect timing match for doing COG/HUB memory transfers.
I guess another approach would be to just use the SPI flash for XMM support in GCC and let graphics totally own the SDRAM but I think that would generate much slower C performance.
Any ideas?
The SDRAM driver will need a cog, though it could be melded with a display driver, since it needs memory faster than anything else.
The reason there's only one SDRAM is because the chip can't transfer data between the hub and pins any faster than 16 bits per clock. Think how you can do a RDQUAD/WRQUAD every 8 clocks and how a quad has 8 words in it. You could hook up another SDRAM to get a full 32-bit data path, and that would help for video output on the same cog, but you're still limited to transferring only one word per clock between cog and hub RAM. The advantage of another SDRAM would only be for video displaying, not video writing, since video write data will likely be coming from other cogs via the hub. The more holistic approach is to just have one SDRAM chip with a 16-bit data path.
Those L-C circuits on the pin group power supplies are to reduce noise for those pins so that analog I/O will be cleaner.
There are single SDRAM chips with 32-bit data bus...
On the other hand, it'd be nice to have a lot of free pins...
Actually, if you were doing Z80 emulation, maybe an 8-bit data bus would be good...
BTW: I, personally, like the leadless smt option for the module...
That said, it would also be nice to have a similar board without the SDRAM and with more of the IO brought out on the header(s).
For experimentation and low volume applications these modules will likely be the most simple way to use the P2.
C.W.
I think quad SPI or octal SPI would serve many people's needs for external memory devices, without the pin penalty.
The Ethernet interface I'm looking at is either 12 or 20 pins in width, so that will gobble up some I/O to implement.
True but we don't have a built-in controller that will do the setup fast enough to take advantage of accessing a long at a time. That being said ....
We could use the CLUT for a line-at-a time instruction read cache since we have full control over the pointer(s) and the direction of pop (FIFO -vs- STACK). Writes could be done with small read-modify-write bursts. One problem with data access is in modifing the byte-lane according to the lower 3 bits, but it wont be so bad. Another problem is that we may exhaust COG memory before a working solution is in place.
BTW, these ideas are "obvious" usage of data structures and machine interface.
I would be happy to just load the user program from flash into SDRAM and use Single Memory XMM. Of course if you could do that, then using sdcard files as program storage is just a few steps away. I see some utility in just running code from flash though. In any event, you could probably put bootloader into flash and switch to sdcard for normal operation.
Right. That is how it will probably work best: the video display cog handles the SDRAM and also serves other cogs SDRAM data via hub RAM.
Is it implemented in our fpga emulator?
I can see one cog doing video and memory for low-res video, like NTSC.
Hard for me to imagine doing this with 1080p and 8-bits per pixel though...
Is there a way to only get 16bit reads fast with INA?, don't want wasting cycles to shift and merge in two 16bit reads for 32bit data etc.
I mean, why take up all that chip space at the expense of built in RAM to have 96 IOs that take up space for comparator, PWM, analog, counters, video support and all those other functions for each pin if half the pins on the chip are just going to be used for digital IO? We might have had a 48 'super' prop pins and 46 plain data pins and have more room on the die for memory. thoughts?
P0-P46 are there, plus TX/RX are P91/P92, plus the 4 pins going to the flash are P87-90. So the SDRAM 39 pins from P47-86?
For a lot of applications it's worth it. For those that need more I/Os and less memory, then they need a different board without the sdram
Seems they put ball package SDRAM mounting directly on top of the Broadcom chip.
It's called package-on-package... I don't know if that's an option here, but would make things even smaller....
I see this question more like: why would you waste so much chip space making sure every pin has a big honkin' IO pad when limiting the IO to a subset of pins would free up room for more SRAM?
I've considered idea this many times. My conclusion is that it's a Chip chip thing. I would much rather have more on-chip memory (how much more being possible is debatable), but the design couldn't claim to support any function on any pin.
Propeller is generally about simplicity and flexibility. In this case Chip chose hardware flexibility over more on-chip memory.
Still, it's kinda like having a Swiss army knife... You may never use all the different blades, but it's nice to have them anyway...
- P0-46 I/O pins
- /RST, TX, RX
For a total of 50 prop pins
as well as VDD3.3 and GND
Combining this info with Chip's presentation showing the 64 pin PCI-e 4x connector suggests 14 pins for VDD3.3 and GND
If feasible, it would be nice to bring the four pins used for the SPI flash to the connector as well.
Crosslink for More Prop 2 Module Details: http://forums.parallax.com/showthread.php/147772-What-type-of-boards-will-be-available
Both sound like good ideas.
Rather than just back-side SMD, you could bring to holes around the edges, and then a final route-pass leaves half-a-hole, which gives a vertical solder path, for manual soldering, and also allows inspection of SMD reflow.
If room allows, and you have micro vias, then a top-bottom via can give a redundant path, in case the plating corner has stress failures.
AMP Connector that is 144 pins, right-angle, and $6.35 for 1, $4.23/ea in 500 qty.