When using CALL & RET instructions, you can save and restore the Z & C flags using the same instruction - just use the WC and WC modifiers on the CALL/RET instructions. On the CALL, the cog return address is saved at the Destination in bits 8..0 and the Z & C (if WZ & WC are specified) in bits 10 & 9 respectively.
It is that simple!!! Thanks Chip
call #routine wz,wc ' call a subroutine and save the Z & C flags
...
routine ...
...
routine_ret ret wz,wc ' return and restore the Z & C flags
Caution: Because the Z & C flags are stored in bits 10 & 9 of the destination, they in fact are bits 1 & 0 of the D field. Therefore, you cannot save the return address with flags into a CALL instruction as the D field would be corrupted. This works fine in a JMP or RET instruction because the D field is not otherwise used.
This one is more of an interesting feature, but a trick nonetheless...
There is a new instruction pair, SUBR and CMPR (R=reverse) which perform D=S-D
Here is a trick to using CMPR (from Chip's P2 ROM Monitor)...
'checking for visible characters in the ascii chart from $20..$7E (" ".."~")
cmp x,#" " wc 'visible chr? set c if <" "
if_nc cmpr x,#"~" wc 'visible chr? set c if >"~ "
if_c jmp #:loop 'not visible if c set
Now the interesting part is that this instruction pair's opcode is also shared with SETINDx instructions. For a long time I remained convinced that there was an error in the decoding of these instructions despite Chip's assurance there was not. Of course I was wrong and here is why...
The SETINDx instructions always have WZ, WC & WR as =0. The SUBR always has WR=1. No problems here.
But, CMPR has WR=0 (i.e. NR). So how can this be shared with SETINDx?
Then penny dropped. You cannot have a useful CMPR without either WZ and/or WC.
So, SETINDx required WZ=WC=WR=0 and CMPR requires either WZ=1 and/or WC=1, and SUBR requires WR=1.
Very smart decoding Chip
BTW: pnut does not enforce the setting of WZ or WC.
Comments
When using CALL & RET instructions, you can save and restore the Z & C flags using the same instruction - just use the WC and WC modifiers on the CALL/RET instructions. On the CALL, the cog return address is saved at the Destination in bits 8..0 and the Z & C (if WZ & WC are specified) in bits 10 & 9 respectively.
It is that simple!!! Thanks Chip
Caution: Because the Z & C flags are stored in bits 10 & 9 of the destination, they in fact are bits 1 & 0 of the D field. Therefore, you cannot save the return address with flags into a CALL instruction as the D field would be corrupted. This works fine in a JMP or RET instruction because the D field is not otherwise used.
There is a new instruction pair, SUBR and CMPR (R=reverse) which perform D=S-D
Here is a trick to using CMPR (from Chip's P2 ROM Monitor)...
Now the interesting part is that this instruction pair's opcode is also shared with SETINDx instructions. For a long time I remained convinced that there was an error in the decoding of these instructions despite Chip's assurance there was not. Of course I was wrong and here is why...
The SETINDx instructions always have WZ, WC & WR as =0. The SUBR always has WR=1. No problems here.
But, CMPR has WR=0 (i.e. NR). So how can this be shared with SETINDx?
Then penny dropped. You cannot have a useful CMPR without either WZ and/or WC.
So, SETINDx required WZ=WC=WR=0 and CMPR requires either WZ=1 and/or WC=1, and SUBR requires WR=1.
Very smart decoding Chip
BTW: pnut does not enforce the setting of WZ or WC.