Yet Another Sigma A/D question

David Buckley

I've read extensively on the forum on this issue. But I cant find an answer to a particular question.

Going all the way back to Chips first posting on the issue, he used quite big caps (0.1uF) and low value resistors, but was clocking at 80MHz and had the now-oft-repeated warnings that the componenets need to be surface mount right on top of the prop, and not a DIP prop at that. The reasoning for this is the fact that the loop length is 12.5nS.

So, the question, if instead of having FREQ set to 1, and clocking the counter at 80MHz, I clock the counter more sedately, at perhaps 1MHz, will this remove the reliance on great layout and SMT components and Prop? I'm comitted to DIL, and only need low speed conversion, and 10 bits would be entirely adequate (heck, I'd settle for 8!) but I'd like a little more range than the simpler arrangement suggested by Duane in this thread.

From the Sigma Delta Calculator, it looks like it might work...?

Rayman

It's an interesting idea... maybe it would work, but I think you'd need bigger value capacitors or resistors.

If you're OK slow, you can just do the RC-time approach...

Mike Green

You have to change the system clock frequency from 80MHz to something else slower. The feedback cycle runs at the system clock frequency. All you have to do is reduce the PLL multiplier. If you use PLL1X with the standard (5MHz) crystal, the system clock frequency will be 5MHz which is much more tolerant of longer leads and the DIP package. Remember that the Propeller I/O transistors still have very fast transition times (on the order of ns), so there will be some ringing of the signals and you can't be too sloppy with the wiring ... and 5MHz still isn't really slow.

If you need execution speed, you can switch back and forth between PLL1X and PLL16X as you do measurements and computation. Look in the Propeller Manual for how to do this.

lonesock

Just doing a slower sample-rate will let the counters integrate over a longer time period, resulting in less noise. Do you have a demo board or a protoboard where you can just try it? Integrate over your entire sample period and just throw away the low bits. (I do something similar in http://forums.parallax.com/showthread.php/130779-EasyADC-call-for-feedback to always align the output data to 16 bits.)

Jonathan

Christof Eb.

Hi David,
when I studied sigma delta ADC on the propeller some time ago, I found the following:
There is a certain band of voltage where the electronics which are (mis-?) used as comparator cannot decide, whether this is low of high. Each decision in this band is completely reigned by chance. As far as I remember there wasn't even a gaussion distribution. If you use a bigger capacitor and lower frequency, then the time inside this band is longer. So there is no benefit of slower conversion in comparison to faster conversion and averaging many results. 10 bits resulution is not possible. 7 or 8 bits might be.
The supply-voltage is used as reference. Of course this will vary inside the propeller depending on power demand of the running cogs and the outputs. This is a second limit for the adc.
So if you need a reliable adc you will have to use an external chip as the Parallax boards do.
Christof