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ADC to DAC

dynoportdynoport Posts: 7
edited 2013-03-19 14:57 in BASIC Stamp
Hello,

I have an 8 bit ADC (0831) connected to a BS2 monitoring the location (steps) of the 10K Pot. I am trying to now incorperate a DAC 12 bit (AD667KN), hoping to output a scaled value of 0-10+Volts. How (or) can I connect the the AD667KN to achieve 0-10 volts? Any suggestions?

Comments

  • Chris SavageChris Savage Parallax Engineering Posts: 14,406
    edited 2013-03-12 13:24
    Welcome to the forums! It would help to get a response if you could include a link to the datasheet for the DAC you're referring to. This would provide the needed information to formulate a suggestion or answer.
  • dynoportdynoport Posts: 7
    edited 2013-03-12 14:16
    Thanks Chris.
    I will include a link to the datasheet. Although I have backed up a few steps as I was not clear on the whole DAC things (not that I have it all down yet either). I am working through Chapter #4: Basic Digital to Analog Conversion
    BUILD A RESISTIVE LADDER NETWORK using the Homework board (BS2)

    After completing the analog to digital portion and the digital to analog ( 4-bit R-2R DAC). After completing the Chapter I wanted to use a potentiometer to send a signal to the ADC and then use the resistive ladder DAC to create an analog output 0-3V. At this time I have given up on the 12 bit converter (for now). Unless its easier than the R-2R-DAC ladder.
    How do I setup the the bs2 to complete this task?

    DAC datasheet http://pdf1.alldatasheet.com/datasheet-pdf/view/48134/AD/AD667KN.htmldatasheet.pdf
    CtYVrly5coVF7OH4M7l
    1024 x 431 - 30K
  • dynoportdynoport Posts: 7
    edited 2013-03-12 17:06
    Here is the code I am using:
    ' {$STAMP BS2}
    ' {$PBASIC 2.5}

    '[Declarations]
    adcBits VAR Byte
    v VAR Byte
    r VAR Byte
    v2 VAR Byte
    v3 VAR Byte
    n VAR Nib

    '[Initialization]
    CS PIN 0
    CLK PIN 1
    DataOutput PIN 2

    DEBUG CLS 'Start display.
    DEBUG CLS, "DAC Nibble Values", CR
    DEBUG "Decimal Binary DVM", CR

    ' [Main Routine]
    FOR n=0 TO 15

    GOSUB DAC
    GOSUB ADC_Data
    GOSUB Calc_Volts
    GOSUB Display
    NEXT
    STOP

    '[Subroutines]
    DAC:
    DIRB = 15
    OUTB = n
    RETURN

    ADC_DATA:
    LOW CLK
    LOW CS
    PULSOUT CLK, 210
    SHIFTIN DataOutput,CLK,MSBPOST,[adcBits\8]
    HIGH CS
    RETURN

    Calc_Volts:
    v=5*adcBits/255
    r=5*adcBits//255
    v2=100*r/255
    v3=100*r//255
    v3=10*v3/255
    IF (v3>=5) THEN v2=v2+1
    IF (v2>=100) THEN
    v=v+1
    v2=0
    ENDIF
    RETURN

    Display:
    DEBUG DEC2 n, " ", BIN4 n, " "
    DEBUG DEC1 v, ".", DEC2 v2, " Volts", CR

    IF (IN15= 1) THEN
    DEBUG HOME,CR, "Decimal value to DAC: ", DEC3 n
    DEBUG ",8-bit binary value,",BIN8 adcBits
    DEBUG ",Decimal value,",DEC3 adcBits
    DEBUG ",DVM Reading,"
    DEBUG DEC1 v, ".", DEC2 v2, ",Volts!",CR
    ELSE
    RETURN
    ENDIF
    RETURN
  • Chris SavageChris Savage Parallax Engineering Posts: 14,406
    edited 2013-03-13 08:22
    You can certainly use an R2R ladder for DAC output and the op-amp will buffer the output for you. I am confused by your potentiometer on the output of the DAC though. Picture this...you have the potentiometer set to VSS and the DAC tries to output max voltage. Now your op-amp (and posibly the potentiometer) will be damaged. I thought the potentiometer was going to the input of the ADC?
  • dynoportdynoport Posts: 7
    edited 2013-03-13 10:03
    I see your point. I do want it to connect to the ADC. That's where I am lost. The Potentiometer in the first lesson connected to the V posative. When we incoprated the DAC ladder I removed the Pot and placed the ladder on the pin I connected the pot to. So I am unclear where the pot needs to go to make it work.
  • dynoportdynoport Posts: 7
    edited 2013-03-14 15:35
    I have made some progress, but I am still having some problems. I see that in the ckt below and in the previous posts the output of the DAC tied back into the ADC so I could view it through the stamp software.
    I have now changed from a 4 bit to an 8 bit R2R ladder (see the diagram) but when I run a sweep of the 255 bits the value keeps counting to full scale way before the last bit. I changed the VAR from nib to byte, and the sweep from DIRB (P4-7) to DIRH (P8-15) using OUTH but the problem still exists. I have supplied the code that I am using. Stamp Code.txt
    DAC1.jpg


    Can someone tell me why this code does not work to sweep through and why the voltage output of the ladder DAC repeats and does not step correctly.

    Thanks
    1024 x 506 - 37K
  • SapphireSapphire Posts: 496
    edited 2013-03-14 20:22
    There are two problems with your circuit. First, the LM358 is not a rail-to-rail op-amp, and needs Vcc to be at least 1.5v more positive that then common-mode voltage. So anytime your R2R network exceeds 3.5v, it will pull the output to Vcc. If you want to use this op-amp in this configuration, you are going to need a higher Vcc for it. Second, the extra 2k resistor connected between the non-inverting input and Vss is not normally used in a R2R DAC. I looked at the souce you referenced, and although it is shown there, it was done to load the network and limit the maximum output voltage. But in doing so, it will change the output values.

    I would suggest you remove the 2k resistor and the op-amp. Then using a volt meter, measure the voltage you get at the top of the ladder as you change the input values. It should swing from 0v with 00h in to 5v with FFh in. If so, your ladder network is okay. If not, then you may have a resistor swapped somewhere along the network. Once you have that working, you could connect it directly into the ADC0831 because that is a high-impeadence input and will not load down the network.
  • dynoportdynoport Posts: 7
    edited 2013-03-15 18:21
    Sapphire

    Thanks for the help. It worked. The only thing I see is the 5V on the ADC is 3.166V on the DAC output. I assume the resistor ladder reduced the voltage?! 0V=0V The ladder steps and does not repeat a voltage earlier than step 255. The pot movement creates stable output readings on the DVM.:thumb:

    Here is the code I had to use and a schematic.
    DAC3.jpg
    Stamp code2.txt

    Is the buffer op amp needed to buffer the DAC output to a data logger?
    1024 x 506 - 31K
  • SapphireSapphire Posts: 496
    edited 2013-03-15 19:50
    The 3.166v limit from the ADC may still be from the extra 2k ohm resistor shown on the right of the schematic. That will load down the output and limit the upper voltage.

    If your data logger has a high impedance input, you shouldn't need the op amp buffer.
  • dynoportdynoport Posts: 7
    edited 2013-03-19 14:57
    OK, now that I have the ladder R2R working correctly with the potentiometer, I would like to complete this process (mainly for myself). Remove the R2R ladder and replace it with the DAC AD667KN (http://www.alldatasheet.com/datasheet-pdf/pdf/48134/AD/AD667KN.html)
    I am fairly certain about the DB0-DB11 connections to an 8 bit system but I am not sure how to setup or interpret the A0-A3 from the datasheet. La-mien's terms.

    In addition to that Sum JCT and BIP Off.

    The goal is to replace the R2R ladder with the DAC chip, with an output of 0-5V.

    Thanks in advance for all the help.
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