David
Do you know how the LEDs are connected on the DE2 board (some schematic?). Are the LED pins not shared with the Switch input pins in the DE2 emulator?
Confirmation by the DE0-NANO is for me one instance higher than confirmation by Chip (sorry Chip )
Confirmation by a real P2 chip would be again one instance higher.
David
Do you know how the LEDs are connected on the DE2 board (some schematic?). Are the LED pins not shared with the Switch input pins in the DE2 emulator?
Andy
Yes, the LEDs and the switches are on the same pins. Maybe that's what is causing the problems.
Here is the description I got of the switches and LEDs on the DE2-115 board. I'm not sure how a single pin can be used in this way but I guess this explains why my blink program doesn't work.
The 18 slide switches are mapped to P49..P32.
The 18 red LEDs are driven by P49..P32 outputs, though the inputs will always read the slide switch states.
How can a single pin have two separate signals on it?
Yes this is the problem! Your LEDs will always show the inverted states of the switches with th code from post #2.
This is only possible on an FPGA emulation. The Verilog code knows if it is a read or a write and selects different FPGA hardware pins (I guess).
Andy
Hmmm... I wonder if we can get Chip to change this. It would be more useful if the FPGA behaved the same as the chips will eventually. Maybe he could move the switches to different P2 pins.
Even if it is correct ---> It is not correct for me as that don't show if Chip have BUG in description else hardware ---> It only show how existing hardware function.
Confirmation by the DE0-NANO is for me one instance higher than confirmation by Chip (sorry Chip )
Confirmation by a real P2 chip would be again one instance higher.
Here is the description I got of the switches and LEDs on the DE2-115 board. I'm not sure how a single pin can be used in this way but I guess this explains why my blink program doesn't work.
How can a single pin have two separate signals on it?
On the FPGA, I sent the OUT/DIR signals to the LEDs and read the INs from the switches. It's not same-pin-bound like the chip will be.
Comments
Thanks,
David
DAT org 0 mov dira,#$FF getcnt r2 add r2,rate loop mov r1,pina xor r1,#$FF mov pina,r1 waitcnt r2,rate jmp #loop rate long 30_000_000 r1 long 0 r2 long 0AndyDo you know how the LEDs are connected on the DE2 board (some schematic?). Are the LED pins not shared with the Switch input pins in the DE2 emulator?
Andy
Sapieha
Confirmation by the DE0-NANO is for me one instance higher than confirmation by Chip (sorry Chip
Confirmation by a real P2 chip would be again one instance higher.
Andy
How can a single pin have two separate signals on it?
This is only possible on an FPGA emulation. The Verilog code knows if it is a read or a write and selects different FPGA hardware pins (I guess).
Andy
Hmmm... I wonder if we can get Chip to change this. It would be more useful if the FPGA behaved the same as the chips will eventually. Maybe he could move the switches to different P2 pins.
Yes -- I looked on SCH --- It is different pins FPGA use on LEDS and SW's
Even if it is correct ---> It is not correct for me as that don't show if Chip have BUG in description else hardware ---> It only show how existing hardware function.
On the FPGA, I sent the OUT/DIR signals to the LEDs and read the INs from the switches. It's not same-pin-bound like the chip will be.