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P2 projects? — Parallax Forums

P2 projects?

David BetzDavid Betz Posts: 14,516
edited 2013-01-19 05:19 in Propeller 2
Things have gotten kind of quiet in here. What sorts of things are people working on with their DE0-Nano and DE2-115 FPGA boards? I've been plugging along with PropGCC and have recently been joined by Eric Smith who is the project lead for the PropGCC P2 effort. I've checked in a bunch of new stuff but haven't made a new release yet. Mainly, I've gotten SD support working and have added P2 support to propeller-load making p2load unnecessary at least for C/C++ program loading. What are other people doing with their boards?

Comments

  • SapiehaSapieha Posts: 2,964
    edited 2013-01-15 08:45
    Hi.

    I only test instructions and program snippets before NANO PCB arive
  • David BetzDavid Betz Posts: 14,516
    edited 2013-01-15 09:16
    Sapieha wrote: »
    Hi.

    I only test instructions and program snippets before NANO PCB arive
    I'm looking forward to Chip's DE2-115 board so I can work on XMM modes for P2. Unfortunately, I can't do that with the DE0-Nano since I need a COG to run the cache driver in addition to the one running the user program.
  • SapiehaSapieha Posts: 2,964
    edited 2013-01-15 09:21
    Hi David.

    I can only dream up on DE2-115.
    Happy I have NANO with help of Bill.

    David Betz wrote: »
    I'm looking forward to Chip's DE2-115 board so I can work on XMM modes for P2. Unfortunately, I can't do that with the DE0-Nano since I need a COG to run the cache driver in addition to the one running the user program.
  • David BetzDavid Betz Posts: 14,516
    edited 2013-01-15 09:22
    Sapieha wrote: »
    Hi David.

    I can only dream up on DE2-115.
    Happy I have NANO with help of Bill.
    I may try to integrate external memory access into an XMM kernel. I think Ross offers that option in Catalina. It would be nice not to require a second COG. However, I'm not sure the code will fit.
  • Bill HenningBill Henning Posts: 6,445
    edited 2013-01-15 10:21
    That would be cool.

    Hopefully Chip will have time to add support for the on-board SDRAM on the Nano in the near future.
    David Betz wrote: »
    I may try to integrate external memory access into an XMM kernel. I think Ross offers that option in Catalina. It would be nice not to require a second COG. However, I'm not sure the code will fit.
  • David BetzDavid Betz Posts: 14,516
    edited 2013-01-15 10:26
    Bill Henning wrote: »
    That would be cool.

    Hopefully Chip will have time to add support for the on-board SDRAM on the Nano in the near future.

    Sapieha's board for the Nano has a SPI flash chip that will probably be easier to use than SDRAM. I think SDRAM support is going to require its own COG to handle things like refresh.
  • Bill HenningBill Henning Posts: 6,445
    edited 2013-01-15 11:13
    Modern SDRAM's can be configured to self refresh when not selected :)

    Chip added an XFER instruction to burst up to 64 longs from SDRAM to the CLUT, which could be flushed to the hub, so by restricting the size of FCACHE or FLIB the requirement for a second cog should be avoidable.

    Besides, there are other uses for SDRAM such as high resolution - high color video drivers :)
    David Betz wrote: »
    Sapieha's board for the Nano has a SPI flash chip that will probably be easier to use than SDRAM. I think SDRAM support is going to require its own COG to handle things like refresh.
  • David BetzDavid Betz Posts: 14,516
    edited 2013-01-15 11:18
    Bill Henning wrote: »
    Modern SDRAM's can be configured to self refresh when not selected :)

    Chip added an XFER instruction to burst up to 64 longs from SDRAM to the CLUT, which could be flushed to the hub, so by restricting the size of FCACHE or FLIB the requirement for a second cog should be avoidable.

    Besides, there are other uses for SDRAM such as high resolution - high color video drivers :)
    HiRes video would be nice. Could you do that with a single COG?
  • Bill HenningBill Henning Posts: 6,445
    edited 2013-01-15 11:40
    David Betz wrote: »
    HiRes video would be nice. Could you do that with a single COG?

    I belive so. I am eagerly awaiting documentation for the XFER and video related instructions - and all other new features/instructions ofcourse :)
  • David BetzDavid Betz Posts: 14,516
    edited 2013-01-15 11:47
    Bill Henning wrote: »
    I belive so. I am eagerly awaiting documentation for the XFER and video related instructions - and all other new features/instructions ofcourse :)
    Yes, information on the SDRAM support facilities will be very interesting!
  • jazzedjazzed Posts: 11,803
    edited 2013-01-15 13:46
    Bill Henning wrote: »
    Modern SDRAM's can be configured to self refresh when not selected :)

    As I recall P2 will require 3.3V compatible IO. Which device were you considering that will work with self-refresh during active operation?
  • Bill HenningBill Henning Posts: 6,445
    edited 2013-01-15 15:50
    The P2 supports 1.8V - 3.3V I/O, however I believe the DE0-Nano uses the IS42S16160B-7 SDRAM, which has 3.3V I/O

    I was referring to self refresh when the SDRAM is not selected, I will manually refresh it as needed - it's not a big deal.
    jazzed wrote: »
    As I recall P2 will require 3.3V compatible IO. Which device were you considering that will work with self-refresh during active operation?
  • jazzedjazzed Posts: 11,803
    edited 2013-01-15 16:32
    Bill Henning wrote: »
    The P2 supports 1.8V - 3.3V I/O, however I believe the DE0-Nano uses the IS42S16160B-7 SDRAM, which has 3.3V I/O

    I was referring to self refresh when the SDRAM is not selected, I will manually refresh it as needed - it's not a big deal.

    Chip mentioned 1.8V IO being much slower than 3.3V IO before. Wonder if it's still true ....

    Yes, I have some of those around here. The amount of code required to make it work is more than I would like, but the burst nature is very useful for a cache (and other things). With more RAM we can do better set associative caching. I remember Chip saying something similar to "the SDRAM is like a train to get started".

    I don't plan to design any P2 "platform hardware" this time as I'm sure Parallax hardware will suit my needs perfectly until I'm ready design a product prototype. Besides, I have enough to do already.

    I do have some interesting product ideas though (not related to micro-controller platforms at all).
  • Roy ElthamRoy Eltham Posts: 3,000
    edited 2013-01-15 18:38
    I recall Chip telling me that some of the advanced I/O features don't work if it's not 3.3v. Like the ADC/DAC, etc... might include the SDRAM stuff too.
  • User NameUser Name Posts: 1,451
    edited 2013-01-17 23:56
    David Betz wrote: »
    Things have gotten kind of quiet in here.

    Your observation produced a twinge of guilt. I should be writing code or documentation. Instead I'm working night and day on ARM and P1 projects. But I read every single post on the P2 forum and admire all that has been achieved in such a short time.

    Too many chips, too many interests, and not enough time!!
  • pik33pik33 Posts: 2,388
    edited 2013-01-18 00:27
    No time. I am studying and doing researches for my PhD degree. My faculty on the university just bought some DE2-115 for student's laboratory, so now I can have acces to DE2-115, but no time to play.

    One good project which can be done with P2 is an one chip retrocomputer. With 10x more processing power than P1 and ~128 kB of RAM I think all 8-bit computers can be emulated with it.
  • TubularTubular Posts: 4,705
    edited 2013-01-19 05:19
    I'm working on some commercial applications, but really need the counters and/or video generation documented to get going. I have toyed with the idea of bit banging composite video, since I figure we now have a plentiful 3840 instructions per video line, but really its better to wait, isn't it?

    If the planets align I'm hoping to put together an interesting demo system based around a Grandstream GXV3500 video to IP converter,combining its RS485 and digital signals to interact with a DE2, some I/O, and its development PC.

    Like others around here I have a few neat ideas for demonstration boards. It's going to be a blast once it all gets going.
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