That's terrible. Somewhere in my archives I have schematic for a 4 bit counter done with tubes. The output is decoded and displayed as one of ten neon lamps. Which might as well be one of the ten digits in a nixie tube as far as I can tell. No solid state diodes anywhere.
It looks like some of the diodes where used for a full-wave rectifier for the power supply, and the other diodes were used for decoding -- probably to drive the display. He only worked on it for 7 years. Maybe he's not done, and the diodes will eventually be replaced by tubes.
But you do not have a ripple counter here. I'm not sure exactly what it is..
Looks to me like a shift register, running a single active bit, and then the 7 seg decode is a simple Diode-Rom from each Digit-bit.
We have also done direct 7 segment counters in SPLDs, those used 7 registers and a state engine design, where the next state bit pattern, was the desired 7 Seg pattern. This eliminates (swallows?) the '7 segment rom'
I think we even managed to fit Up/Dn into a 22V10.
@jmg:. ..Why? Because I want it to be a challenge. I've learned more about analog circuitry in this project than hours of classes could give me. That is why I'm doing it the old fashioned way.
You should run this block/cell into Spice, and learn even more
eg I ran it up, and Spice says the trigger Caps can go down to 220pF on a RTDL version, and down to < 100pF on a RTTL version.
Vcc can also go down to between 1.2 and 1.5V, and the Clock drive can be of lower amplitude.
Just checked it can go to 250mV on the RTTL version.
In a version where I replaced the steering diodes (RTDL) with steering transistors (RTTL), it even clocked down to 1.1V with low swings on the Q , /Q lines.
Spice can also test the top clock speed, but in your app, speed is not really an issue ...
jmg,
What circuit exactly are you simulating? There is the one from microcontrolled's post #1, or the whole contraption (!) from post #17, and a little piece I pulled out in post #29. You say it is a shift register and he wants it to be a binary counter, and some part of it is now working as expected with the new resistor values.
I created the schematic I posted in LTspiceIV, however, when you run the simulator it doesn't work correctly even though it does if you actually build the circuit (probably due to the fact it relies on an exploit, but I could just be making a noob spice mistake). So, yes, if you want to fix up the schematic to be simulator-compatible and actually run it, here it is: http://microcontrolled.com/FinalClockSchematic.asc
Thanks for the explanation, microC. I was confused by that relay (I am easily confused). It looked to me like the relay coil was turned on by the transistor Q24, but the power to drive the transistor would not be present until the relay was activated. Kind of a no-action situation. But I'm doubtless misunderstanding something there.
I'll take a rain check. I see you've marked the tread "solved", so maybe that means you want to go back to the drawing board, or the bread board, and think it thru in your own way. Good luck with it!
jmg,
What circuit exactly are you simulating? There is the one from microcontrolled's post #1, or the whole contraption (!) from post #17, and a little piece I pulled out in post #29. You say it is a shift register and he wants it to be a binary counter, and some part of it is now working as expected with the new resistor values.
I tried upload of the example, but the file manager barfed on the LT Spice ASCII files .asc and also .asc_ ??
Following #43 I have now added as a ZIP
This has 2 files, the original RTDCL_FF.asc
and my just-for-fun variant, RTTCL_FF_RT.asc which has a symmetric 2*Vbe swing and uses steering transistors in place of diodes.
@Tracy: I marked the thread as "solved" so that I didn't get anyone who didn't read over the rest of the thread trying to answer the original question. The line that goes out of frame in the screenshot you posted (the one on the left out of the 2) is tied to VDD. The wire that runs along the top of the latches is what is switched off. The relay is drawn backward because Spice didn't have a relay component so I just "made one" that was visually correct for the schematic. The relay, when latched, shuts off the power that latches it. It doesn't seem like it would work, but I tested this, and it does.
Comments
Looks to me like a shift register, running a single active bit, and then the 7 seg decode is a simple Diode-Rom from each Digit-bit.
We have also done direct 7 segment counters in SPLDs, those used 7 registers and a state engine design, where the next state bit pattern, was the desired 7 Seg pattern. This eliminates (swallows?) the '7 segment rom'
I think we even managed to fit Up/Dn into a 22V10.
You should run this block/cell into Spice, and learn even more
http://ltspice.linear.com/software/LTspiceIV.exe
eg I ran it up, and Spice says the trigger Caps can go down to 220pF on a RTDL version, and down to < 100pF on a RTTL version.
Vcc can also go down to between 1.2 and 1.5V, and the Clock drive can be of lower amplitude.
Just checked it can go to 250mV on the RTTL version.
In a version where I replaced the steering diodes (RTDL) with steering transistors (RTTL), it even clocked down to 1.1V with low swings on the Q , /Q lines.
Spice can also test the top clock speed, but in your app, speed is not really an issue ...
Edit: As bonus, all versions of LTSpice I have ever tried work perfectly under Wine on Linux.
What circuit exactly are you simulating? There is the one from microcontrolled's post #1, or the whole contraption (!) from post #17, and a little piece I pulled out in post #29. You say it is a shift register and he wants it to be a binary counter, and some part of it is now working as expected with the new resistor values.
Have fun!
I'll take a rain check. I see you've marked the tread "solved", so maybe that means you want to go back to the drawing board, or the bread board, and think it thru in your own way. Good luck with it!
I tried upload of the example, but the file manager barfed on the LT Spice ASCII files .asc and also .asc_ ??
Following #43 I have now added as a ZIP
This has 2 files, the original RTDCL_FF.asc
and my just-for-fun variant, RTTCL_FF_RT.asc which has a symmetric 2*Vbe swing and uses steering transistors in place of diodes.
I guess the asc file need zipping or something.