You're right about that. It didn't take long to get PropGCC code running on the P2. The main task was modifying GAS to understand the new P2 instructions and I guess you won't have to do that if you wait for Roy's Spin/PASM compiler. I also had to write a new loader because the one that was originally in PNut.exe would only load 2K of code. I suspect Chip has improved it since though. As you say, the remaining work is getting any P1-specific driver code ported over to the P2. I did that last night with the SD driver from PropGCC. I haven't even tried to get the XMM modes working on P2 mainly because I don't have a board that has external memory that is hooked up to the P2. Once I get a SPI flash chip or SRAM hooked up the XMM modes should be pretty easy too.
All of this is mainly due to the fact that the P2 includes most of the P1 instruction set as a subset. In the case of PropGCC, the code generator doesn't emit any non-P2 instructions. A few opcodes have changed like JMPRET but mostly P1 code will compile for the P2. This makes it easy to do a quick port. However, making full use of the new P2 features will require additional thought and work. I haven't started that phase yet.
COGINIT requires a change to COGSET followed by COGINIT. There were only a couple of things I needed to change to get my spin interpreter to compile on pnut.exe, but I am sure there other gotchas here.
COGINIT requires a change to COGSET followed by COGINIT. There were only a couple of things I needed to change to get my spin interpreter to compile on pnut.exe, but I am sure there other gotchas here.
True, I had forgotten about the SETCOG/COGINIT sequence. I buried that in an inline function so I didn't have to think about it anymore! :-)
True, I had forgotten about the SETCOG/COGINIT sequence. I buried that in an inline function so I didn't have to think about it anymore! :-)
This kind of thing would be really valuable if maintained in a separate thread or document on P1/P2 incompatibilities. Is there a complete list of these anywhere?
This kind of thing would be really valuable if maintained in a separate thread or document on P1/P2 incompatibilities. Is there a complete list of these anywhere?
This kind of thing would be really valuable if maintained in a separate thread or document on P1/P2 incompatibilities. Is there a complete list of these anywhere?
JMP/JMPRET/CALL/RET CMPSUB have partial description DJNZ
TJNZ
TJZ WAITPEQ have partial description
WAITPNE have partial description WAITCNT have partial description
Look in my last PDF --- Clored ones are described now
Thanks, Sapieha (& David). Nice to see such a comprehensive document, but I must admit I was just looking for a "cheat sheet" that highlighted the differences from the perspective of porting existing P1 code
Thanks, Sapieha (& David). Nice to see such a comprehensive document, but I must admit I was just looking for a "cheat sheet" that highlighted the differences from the perspective of porting existing P1 code
Ross: I have a summary of instructions if that is any help - it is in spreadsheet format and is in "The unofficial P2 documentation.." thread. Chips has added just a few things since I last updated it.
Ross: I have a summary of instructions if that is any help - it is in spreadsheet format and is in "The unofficial P2 documentation.." thread. Chips has added just a few things since I last updated it.
Hi Cluso.
I'll certainly be studying those - but I don't get that much time to do Propeller work (some of us still have to work for a living ) so it could take me weeks - I stopped keeping in close touch with all the P2 threads once it became clear that an actual chip was still many moons away. My loss, I suppose.
Anyway, the type of document I'm after would be something anyone who has ever programmed a Prop 1 would immediately want to see - if only to gauge how difficult it is going to be to port all their existing code to a Prop 2 - and some of us have tens of thousands of lines of P1 code to port. I don't think many people are going to come to the P2 as their first chip - the largest number of users (at least initially) will probably be P1 users.
I'm a bit surprised no-one has seen the need for such a document yet - but I suppose it is still early days for the P2.
I think most people that are emulating the P2 are still coming to grips with the differences as they try to move their work forward. To really write a doc like that, you need to be comfortable with both chips and I'm not sure anyone is there yet.
I agree that a contrast/comparison/differences document is valuable and will be written at some point.
We may have enought soon with Chips docs and experience growing as they'd are.
You want basic "if i did X on the P1 to do something now I need to do Y in the P2" either on an instruction by instruction basis or a functional level?
For the most part, a whole lot of P1 stuff works as it used to. There are the new pipeline rules on top of that. When no hardware threading is in action, the pipe is deeper requiring some resorting of code to either operate properly or more efficiently. When threading is used, that changes some.
The more specialized a hardware feature is, the more likely the code needs to be modified or rewritten.
This will be like peeling back the onion. It's reasonable to start doing things the P1 way, adapting where needed to get stuff going, then there is the slow process of integrating the new stuff the chip will be able to do, and we don't have all the core docs needed to fully understand that with the pins, video and serial hardware yet.
Eventually, we will need to produce:
1. P2 PASM for the P1 programmer. This is a delta document, followed by "look at all the spiffy new ways to do things!" education document. The P1 programmer will make a learning investment on par with what they did to get themselves boot strapped onto P1 in order to really take advantage of P2.
2. PASM for Noobs. (I know Harpit has his book out) This one will need to target both chips with basic concepts and then fork so that new users can write code reasonably for either chip, but maybe not optimally.
3. Advanced PASM. Probably for P1, existing code will have to suffice for this. Then again, P1 will be here a long time, so maybe that gets written. For P2, we've a lot to learn yet before we can even come close to this document.
I personally am focused on just doing stuff, then once that stuff is happening, attempting it in various ways with the new capabilities as we learn them. Lots of layers in that onion to be peeled back one at a time...
Anyway, welcome to the P2 jungle. It's a lot of fun right now! I hopped back to P1 briefly to advance a project I'm working on and suddenly, it all seems so simple! Amazing how that works.
Edit: Finally, there are parts of the pin I/O that the FPGA doesn't emulate well. Some features, like the video, require some adapter type circuits that are in process, with the NANO seeing the first ones any minute now. Hardware DACS, video, etc... can then be explored.
I personally am itching to know whether or not WAITVID will continue to offer P1 type functionality in addition to the significant P2 enhancements. That's going to determine whether or not we can carry what are now "old school" drivers forward and build on them, or basically just take the frameworks for them and build new. The latter is going to happen anyway because P2 does a lot of new stuff that's going to be challenging. I'm hoping the former can be done fairly easily, because the more roomy P2 would allow simple extensions to those drivers, bringing a lot of good stuff forward and the room to really make it sing right away.
All in time. I feel a bit swamped! The hardest thing for me was not just building up a video environment to then play with the instructions in, which is what I did for P1. On the flip side, I know that monitor cold now and am much better with serial, etc...
Cool doc. Yes the Propeller II is different to the propeller 1.I have been attempting to emulate a 2 core Prop2 in software on RISC OS on my Raspberry Pi (so far in BBC BASIC for prototyping the emulation, once I get it working correctly [including access to the available IO pins on the RPi] I will have to move it to Assembly). Though this is just so I can get a bit of a head start on some projects.
The Propeller 2 apears to be all that we have been waiting for for so long and then some. I am glad that the situation delayed me in attempting to code anything, as the Propeller 2 did change a little (and I am going have to dedicate 1 thread on 1 cog to memory management as the SDRam support, that Chip once mentioned over a year ago, does not apear to have made the cut)
The Propeller 2 is going to be fun to play with, and I have some ideas for projects.And for those who only have a DE0 Nano, I can not even afford that at the moment, so feel good to have that.
...and I am going have to dedicate 1 thread on 1 cog to memory management as the SDRam support, that Chip once mentioned over a year ago, does not apear to have made the cut
I guess it's time for me to confess that I haven't done much P2 work recently. I've been studying how the GCC code generator works in order to add the ability to make use of some of the new P2 instructions. As far as I've gotten so far is using the isob instruction for extracting single bits bitfields. It seems to work but doesn't really offer much code improvement. Is there a clever way to use the new P2 instructions to extract bitfields wider than one bit?
I'm also looking forward to the DE2-115 add-on board that has a SPI flash chip in order to work on XMM support. Any update on when that might be available?
I guess it's time for me to confess that I haven't done much P2 work recently. I've been studying how the GCC code generator works in order to add the ability to make use of some of the new P2 instructions. As far as I've gotten so far is using the isob instruction for extracting single bits bitfields. It seems to work but doesn't really offer much code improvement. Is there a clever way to use the new P2 instructions to extract bitfields wider than one bit?
I'm also looking forward to the DE2-115 add-on board that has a SPI flash chip in order to work on XMM support. Any update on when that might be available?
Did you see the bit-field mover instructions? They are good for handling bytes and words.
We've got the DE2-115 and DE0-Nano add-on boards back, but we found a problem: The DB15 connector had a pin-out description that turned out to be bottom-facing. Those boards are being redone now. When we get them in, we'll build them up and get them out to you guys who have Terasic boards. The Prop2-perspective pin-outs will be pretty much identical across the the Terasic boards. The only difference will be that on the DE0-Nano board, P26, P27, and P28 will be input-only, with push-buttons connected. Both boards will connect to an SDRAM chip over the same Prop2 pins.
We need to build up one of Sapieha's boards to get the configuration file proven for it.
Meanwhile, I've been working on the counter doc's. It's been slow, but it's coming together.
Did you see the bit-field mover instructions? They are good for handling bytes and words.
We've got the DE2-115 and DE0-Nano add-on boards back, but we found a problem: The DB15 connector had a pin-out description that turned out to be bottom-facing. Those boards are being redone now. When we get them in, we'll build them up and get them out to you guys who have Terasic boards. The Prop2-perspective pin-outs will be pretty much identical across the the Terasic boards. The only difference will be that on the DE0-Nano board, P26, P27, and P28 will be input-only, with push-buttons connected. Both boards will connect to an SDRAM chip over the same Prop2 pins.
We need to build up one of Sapieha's boards to get the configuration file proven for it.
Meanwhile, I've been working on the counter doc's. It's been slow, but it's coming together.
Did you see the bit-field mover instructions? They are good for handling bytes and words.
We've got the DE2-115 and DE0-Nano add-on boards back, but we found a problem: The DB15 connector had a pin-out description that turned out to be bottom-facing. Those boards are being redone now. When we get them in, we'll build them up and get them out to you guys who have Terasic boards. The Prop2-perspective pin-outs will be pretty much identical across the the Terasic boards. The only difference will be that on the DE0-Nano board, P26, P27, and P28 will be input-only, with push-buttons connected. Both boards will connect to an SDRAM chip over the same Prop2 pins.
We need to build up one of Sapieha's boards to get the configuration file proven for it.
Meanwhile, I've been working on the counter doc's. It's been slow, but it's coming together.
I went to a conference for a week, had a lot of fun and came back really sick. This is the first weekend I'll feel good enough to fire up my P2 emulation. Was just crappy. Hate that. Don't know about you guys, but I can't hardly think when that happens, and the medicine is a total mixed bag. Sleep becomes possible, but the waking hours are just dead... Mix in work that has to get done, and I got fried. Feeling much better now. The whole company got it too. We took turns holding the fort down this last coupla weeks.
Looking forward to the boards. I'm gonna load up the SD capable DE2 file and start working with that now. About the only thing I finished was the monitor reference doc. A copy is in my blog, and I've sent it to Parallax for Stephanie to edit / format so it's optimal for anyone who needs it.
@Cluso, did you ever get SPIN to a point that's sharable / useful?
It was planed to 03/22.
But I had now possibility to order it already.
I just finished testing the DE0 and DE2 add-on boards. We have 24 DE0 boards and only 13 DE2 boards, because we need more of those special DE2 connectors. We have one extra DE2 board after shipping out current requests. These will ship from Parallax probably on Monday.
Comments
This kind of thing would be really valuable if maintained in a separate thread or document on P1/P2 incompatibilities. Is there a complete list of these anywhere?
Ross.
Most complete PDF.
in first post.
http://forums.parallax.com/showthread.php/144683-Propeller-II-programing-questions-to-Chip
Here is a list I made a while back:
JMP/JMPRET/CALL/RET
CMPSUB
DJNZ
TJNZ
TJZ
WAITPEQ
WAITPNE
WAITCNT
Look in my last PDF --- Clored ones are described now
Thanks, Sapieha (& David). Nice to see such a comprehensive document, but I must admit I was just looking for a "cheat sheet" that highlighted the differences from the perspective of porting existing P1 code
Ross.
I can say You directly --- That document don't exist yet
Ah well - someone will eventually have to write one, I suppose. I won't hold my breath waiting!
Ross.
Hi Cluso.
I'll certainly be studying those - but I don't get that much time to do Propeller work (some of us still have to work for a living
Anyway, the type of document I'm after would be something anyone who has ever programmed a Prop 1 would immediately want to see - if only to gauge how difficult it is going to be to port all their existing code to a Prop 2 - and some of us have tens of thousands of lines of P1 code to port. I don't think many people are going to come to the P2 as their first chip - the largest number of users (at least initially) will probably be P1 users.
I'm a bit surprised no-one has seen the need for such a document yet - but I suppose it is still early days for the P2.
Ross.
I think most people that are emulating the P2 are still coming to grips with the differences as they try to move their work forward. To really write a doc like that, you need to be comfortable with both chips and I'm not sure anyone is there yet.
I agree that a contrast/comparison/differences document is valuable and will be written at some point.
We may have enought soon with Chips docs and experience growing as they'd are.
You want basic "if i did X on the P1 to do something now I need to do Y in the P2" either on an instruction by instruction basis or a functional level?
That's just starting.
For the most part, a whole lot of P1 stuff works as it used to. There are the new pipeline rules on top of that. When no hardware threading is in action, the pipe is deeper requiring some resorting of code to either operate properly or more efficiently. When threading is used, that changes some.
The more specialized a hardware feature is, the more likely the code needs to be modified or rewritten.
This will be like peeling back the onion. It's reasonable to start doing things the P1 way, adapting where needed to get stuff going, then there is the slow process of integrating the new stuff the chip will be able to do, and we don't have all the core docs needed to fully understand that with the pins, video and serial hardware yet.
Eventually, we will need to produce:
1. P2 PASM for the P1 programmer. This is a delta document, followed by "look at all the spiffy new ways to do things!" education document. The P1 programmer will make a learning investment on par with what they did to get themselves boot strapped onto P1 in order to really take advantage of P2.
2. PASM for Noobs. (I know Harpit has his book out) This one will need to target both chips with basic concepts and then fork so that new users can write code reasonably for either chip, but maybe not optimally.
3. Advanced PASM. Probably for P1, existing code will have to suffice for this. Then again, P1 will be here a long time, so maybe that gets written. For P2, we've a lot to learn yet before we can even come close to this document.
I personally am focused on just doing stuff, then once that stuff is happening, attempting it in various ways with the new capabilities as we learn them. Lots of layers in that onion to be peeled back one at a time...
Anyway, welcome to the P2 jungle. It's a lot of fun right now! I hopped back to P1 briefly to advance a project I'm working on and suddenly, it all seems so simple! Amazing how that works.
Edit: Finally, there are parts of the pin I/O that the FPGA doesn't emulate well. Some features, like the video, require some adapter type circuits that are in process, with the NANO seeing the first ones any minute now. Hardware DACS, video, etc... can then be explored.
I personally am itching to know whether or not WAITVID will continue to offer P1 type functionality in addition to the significant P2 enhancements. That's going to determine whether or not we can carry what are now "old school" drivers forward and build on them, or basically just take the frameworks for them and build new. The latter is going to happen anyway because P2 does a lot of new stuff that's going to be challenging. I'm hoping the former can be done fairly easily, because the more roomy P2 would allow simple extensions to those drivers, bringing a lot of good stuff forward and the room to really make it sing right away.
All in time. I feel a bit swamped! The hardest thing for me was not just building up a video environment to then play with the instructions in, which is what I did for P1. On the flip side, I know that monitor cold now and am much better with serial, etc...
The Propeller 2 apears to be all that we have been waiting for for so long and then some. I am glad that the situation delayed me in attempting to code anything, as the Propeller 2 did change a little (and I am going have to dedicate 1 thread on 1 cog to memory management as the SDRam support, that Chip once mentioned over a year ago, does not apear to have made the cut)
The Propeller 2 is going to be fun to play with, and I have some ideas for projects.And for those who only have a DE0 Nano, I can not even afford that at the moment, so feel good to have that.
Thank you Chip. :-)
Fixed it, (booted my PC and using FireFox).
It's there. It's just not documented yet.
I'm also looking forward to the DE2-115 add-on board that has a SPI flash chip in order to work on XMM support. Any update on when that might be available?
I work on some tests -- But mostly wait for NANO-PCB and BIN file that support it.
Did you see the bit-field mover instructions? They are good for handling bytes and words.
We've got the DE2-115 and DE0-Nano add-on boards back, but we found a problem: The DB15 connector had a pin-out description that turned out to be bottom-facing. Those boards are being redone now. When we get them in, we'll build them up and get them out to you guys who have Terasic boards. The Prop2-perspective pin-outs will be pretty much identical across the the Terasic boards. The only difference will be that on the DE0-Nano board, P26, P27, and P28 will be input-only, with push-buttons connected. Both boards will connect to an SDRAM chip over the same Prop2 pins.
We need to build up one of Sapieha's boards to get the configuration file proven for it.
Meanwhile, I've been working on the counter doc's. It's been slow, but it's coming together.
Thanks
BTW Is the P2 ready for the Feb shuttle?
I went to a conference for a week, had a lot of fun and came back really sick. This is the first weekend I'll feel good enough to fire up my P2 emulation. Was just crappy. Hate that. Don't know about you guys, but I can't hardly think when that happens, and the medicine is a total mixed bag. Sleep becomes possible, but the waking hours are just dead... Mix in work that has to get done, and I got fried. Feeling much better now. The whole company got it too. We took turns holding the fort down this last coupla weeks.
Looking forward to the boards. I'm gonna load up the SD capable DE2 file and start working with that now. About the only thing I finished was the monitor reference doc. A copy is in my blog, and I've sent it to Parallax for Stephanie to edit / format so it's optimal for anyone who needs it.
@Cluso, did you ever get SPIN to a point that's sharable / useful?
My DE2-115 are now half way to me
It was planed to 03/22.
But I had now possibility to order it already.
I just finished testing the DE0 and DE2 add-on boards. We have 24 DE0 boards and only 13 DE2 boards, because we need more of those special DE2 connectors. We have one extra DE2 board after shipping out current requests. These will ship from Parallax probably on Monday.
My DE2-115 have arived.
Time to start test it.