Excited for the PropII.
Ym2413a
Posts: 630
I can't wait for the new propeller chip to come on out! Been waiting and stalking the forum since 2008.
Seeing the cog emulator is now getting me excited. : ]
Does anyone have an idea when it's going to release as a full chip?
Thanks!
--Andrew L. Arsenault.
Seeing the cog emulator is now getting me excited. : ]
Does anyone have an idea when it's going to release as a full chip?
Thanks!
--Andrew L. Arsenault.
Comments
We are going to be late for the December shuttle, but we'll make the January one, no problem.
If we discover a bug in the logic between now and then, the synthesis company can redo the block for about $4,000. Did that once last week, already.
How long do they take to return a shuttle run?
If it's not confidential, what does a shuttle run cost?
BTW Chip, I have some questions over on the document thread - particularly these (first one is op decoding)
http://forums.parallax.com/showthread.php?144432-The-unofficial-P2-documentation-project&p=1150630&viewfull=1#post1150630
http://forums.parallax.com/showthread.php?144432-The-unofficial-P2-documentation-project&p=1150487&viewfull=1#post1150487
Obviously my suggestion for a new shift instruction is too late - I would rather have the P2.
I had been despartely wanting to ask about the chance of making the December shuttle run, but held off because the shuttle will come when she comes, so to speak, and there's no sense in rushing things at this point after all the careful deliberations and design work.
Nevertheless, I couldn't help wondering over the last couple weeks whether there would have been any merit in going ahead with a shuttle run even with the recently-discovered quirk (that you've already addressed with the rework) because that could have gotten a few test chips into your hands and perhaps those of some advanced users earlier to help flush out any remaining issues, possibly shortening the time to market despite the costs. But $80K, or whatever such a run costs, is a rather steep price to pay for uncertain benefits.
Of course, it's great that you guys are able to do testing with those FPGA "emulators" (you found the above-referenced quirk that way), but it's a bit hard for us mere mortals out here to have confidence in such testing compared to actual/final silicon (considering the differences that surely exist in terms of some electrical and thermal properties and what not). But those shuttle chips will come in due time. I do kind of wonder whether you were tempted to go ahead, though.
Once said shuttle run does happen, though, I wonder how long testing of such chips will take, best-case scenario, wherein no tricky issues are encountered that need characterized. And then, after such verification, how long until mass production and shipping? I wonder if something like 6 months would be typical, again, best-case scenario (and taking into consideration typical fab and packaging lead times). Yeah, yeah, still chomping at the bit, I know (but you have to factor in the number of times I/we didn't ask). Probably 6 months is wishful thinking.
Anyway, thanks again for the update about the shuttle run (and the rework/synthesis), as well as the insight into the design process and openness about some of the costs associated with development (though we would probably be shocked to know all the gory details). And thanks to you Prop-Heads who have invested time, skill and money to do emulation for testing and experimentation, you trail-blazers, you! And thanks to Andrew for asking (what we all were wondering).
Ken Gracey
I have been stalking for quite a bit of time too
I learned to use Spin and the Propeller by buying the Hydra development board which come with a massive and well done manual (now free). I hope that maybe we are going to see a Hydra 2, with simple 3d graphics and good tutorials. (If I recall, Andre' LaMothe had a talk with chip on how to facilitate texture mapping, alpha blending etc... on Prop II).
A few people achieved to reach the limit of the first Propeller (computation and memory). The Propeller II is going to push these walls a lot further!
The scale of this stuff is what stuns me. 7K connections just to "drop it in there" and the pins alone have so many transistors. When it's all debugged, packaged and on a board for us to work with, that seems a given, but for the appreciation I have with what details have been shared with us. There is also the discussion that formed some of the chip too. Many of us had a part in that, small but still a part, and that's special and rare.
Here's to success and a lot of good times ahead!
You might not be so understanding, though, being the focused taskmaster that you are, which, by the way, we do appreciate...because we all want to see the next Prop make it off the drawing board and into our greedy paws. And it's obvious that no one is more committed to keeping things on schedule (as much as reasonably possible) as you are. Thanks again for the useful update!
I think the shuttle costs $63,000. It will take 4 weeks. Then, we'll see if the chip does anything.
If it works, we can get a full mask set made and start production. That will cost, I think, about $159,000.
KeithE asked about boundary scan and BIST. There is none in the chip. We are going to build our own testers to verify the production chips. There's going to be a lot of code to write to make sure that every possible state goes through every flipflop and the logic works properly.
You're welcome, and thank you. My job is to provide the support to see that Chip's job can get done.
I've participated in Propeller 2 design team meetings every Thursday since the end of August, watching the schedule slip week by week while continually approving large purchase orders for tools, synthesis and software. The design progress meetings include our Propeller 2 developers Chip, Beau and sometimes Jeff and Daniel [who are all in different physical locations], along with the synthesis company. The kinds of challenges they face are sometimes quite complex - most recently it was an incompatibility of using two expensive design tools that wouldn't play together nicely. The design team may think I only care about "finishing! completion! fabrication!" but it's actually very important that we finish this project now. It's really amazing to me that we've been able to fund this effort out of pocket so far, but we still have a serious investment in front of us (inventory, characterization, tools, test fixtures, NRE for packaging company testing, training, marketing, GCC, etc.).
The whole Parallax team of 45 has made this possible by continually innovating/educating/supporting our present range of products to drive the financial support for P2 development. They really deserve the satisfaction of bringing it to market, so I want it finished for both our team and for our customers. And especially Chip, who has worked on this since late 2006, often around the clock while raising 0101 kids.
We hope to put these chips in your greedy paws soon.
That's a lot of work - good luck! I'm curious as to how you'll determine your coverage if you're willing to go into the details. It seems like you would have to run gate level verilog sims in order to perform the calculations? I think that Parallax Semi should think about documentation related to this process if your commercial customers are like ours. I guess that you'll be able to run much of the test at speed, and your tester will hopefully be quite cheap compared to what gets used for a typical modern mixed signal chip.
The numbers are quite reasonable, compared to the more bleeding edge.
Of course, given the Silicon works, you have a very nice means to make your own testers, as the Prop 2 is well suited to tester tasks itself!!
Does the full mask set include a reasonable quantity of chips?
I am amazed at the openness of Parallax in sharing the design of the P2 with us all here on the forum. I do hope that our little contributions along the way make up for the delays we have all caused by making the P2 so revolutionary that it takes the market by storm. Sharing the binary of the P2 for the group here to play with is another truly outstanding concept. Within such a short time Bill and others, along with Chip, found a bug. I would expect if we weren't trying to utilise new-found uses for the P2, based on pushing the P1 envelope, it may have not been found during testing.
I finally ordered my DE0-nano today and I will have it in my hands Thursday evening. I had to put off ordering this until I had other things on my plate under control as I knew that I would be too tempted to play before I could afford to spend the time on it.
Ken, when you are ready to put together a writeup for the press, perhaps you may consider putting it on the forum for us all to have some input, including quotes. I think Parallax's openness with the P2 FPGA binary, and the fact that the forum (Bill and others) contributed to the testing and the finding a bug, should be a really defining moment in the release info. This has got to mark a "first" in the industry, and therefore make the article much more newsworthy than otherwise.
Can hardly wait.
But Ken has emphasized the necessity of getting the product out the door many times, and that does seems prudent. For example, you never know when something could happen to interrupt things: a natural disaster, an illness, staff turnover, a vendor change and so on. Such an event could be so disruptive that the project never got finished. On the lighter side, I've also heard that the need to have a life can get in the way, but I suspect that's just a nasty rumor.
Chip, thanks for those additional details on costs and the timing of things. Of course, part of the reason we're curious is to calculate whether some form of "crowdfunding" could play a role (you know the willingness is there on our part if it would be helpful). But it seems that you wouldn't likely get enough chips back from a shuttle run to make that feasible (though perhaps you can pay a little more to get a lot more samples).
Ken, thanks for the additional details about the process. Indeed those are some gory details (even though we could never know the half of it), but they are quite interesting to know. Obviously, you've acquired a lot of technical knowledge or skill at Parallax, even though you are always frank about the limits of your knowledge or ability. But I always enjoy reading your insightful business-related comments. And when, for example, you say something needs to happen "now," we know that such must be the case. So, do carry on. Exciting times, indeed!
It would be neat if we could make a version of Prop2 in 40nm, as it would run at over 1GHz and the entire logic would take less than 0.9 square millimeters. It would cost about $3,000,000 to do, though. I kind of doubt there would be enough believers on Kickstart to make it go.
We currently use Propeller chips to test Propeller chips. It all happens on a little base board that probably cost $15 to make, with a socket adapter that plugs on top of that the chips go into.
Yes, I think that might be hard to raise. And what would you have to give away to get this.
I wish I had the $ to fund this. Maybe I will buy a lotto ticket for the $30M next week - you never know
I personally like that kind of platform independence though. ; ]
Simpler is better IMO.