I think having to set the QUAD window at a QUAD-aligned address is a big pain. Do you guys agree? It keeps the circuitry simple but causes pain for the programmer.
i can see it would be nice to be able to map the quads to any non-contiguous cog locations. however i would still be happy with the restriction they are on a 00 boundary and/or 4 contiguous, depending on the complexity. obviously bill & andy have worked a non-contiguous loop which is very clever for performing the lmm and this will be a major use in high level languages at least.
i will be using readquads for fast loading of binary overlays.
I also have no problem if the one cog address must be quad aligned. This is really a minor problem compared with the LMM code in hub ram, that must be structured in quad packets. I already can see a lot of nops in a GCC generated code.
Could SETQUAD zero the cache registers? That way they would be guaranteed to execute as NOP's first pass through the loop.
In the code below, would the rdquad ever execute? I thought JMPD only had two delay slots - or is my memory playing tricks on me?
There are three instruction slots that must be filled in a single-task JMPD scenario.
I've been thinking about some way to clear the QUADs, as it would make things tidy. On cog startup, they contain the data loaded into $1F4..$1F7.
Does anyone have any thoughts about SETQUAD clearing the registers? I have it set up now so that if you do a SETQUAD $1F8..$1FF the QUADs go into hiding. The hiding case might be a convenient time to clear the QUADs. Does anything think you might want to do a SETQUAD to simply move them, without clearing them?
The reason I'd like the quad cache cleared at a SETQUAD is so that a tight RDQUAD LMM loop will not execute random code.
Andy:
Thanks! Jeez my memory is going... or is that lack of sleep... or lack of cofee...
Chip:
Thanks, I don't know why I had a memory error on that. I'd better check my ECC bits.
How about SETQUAD D wz means clear the cache, without wz does not clear it?
The reason I'd like it cleared is the problem you pointed out many messages ago - the LMM look running random instructions on the first pass through the loop.
That does not work for what I need, I'd have to SETQUAD twice, once to hide it and clear it, and again to repositionit where I need it - every time the LMM2 loop is initiated.
Frankly, I am still trying to figure out a case where it is useful to SETQUAD and NOT clear the cache... I am tring to find a use for that.
I'll make a DE2_115 and StratixIII version a little later. I want to address the QUAD clearing issue and get REPS/REPD so that it works by task, not in general.
The reason I'd like the quad cache cleared at a SETQUAD is so that a tight RDQUAD LMM loop will not execute random code.
Andy:
Thanks! Jeez my memory is going... or is that lack of sleep... or lack of cofee...
Chip:
Thanks, I don't know why I had a memory error on that. I'd better check my ECC bits.
How about SETQUAD D wz means clear the cache, without wz does not clear it?
The reason I'd like it cleared is the problem you pointed out many messages ago - the LMM look running random instructions on the first pass through the loop.
Yes, Bill, I understand that, but there are uses for the cog besides running LMM kernels.
chip, I can't give you any real use examples right now, but I think it would be good if setquad could be called to move the quad mappings without clearing. So if it isn't difficult, I think clearing should be optional somehow. Is the NR/WR bit available?
I'll make a DE2_115 and StratixIII version a little later. I want to address the QUAD clearing issue and get REPS/REPD so that it works by task, not in general.
I'll make a DE2_115 and StratixIII version a little later. I want to address the QUAD clearing issue and get REPS/REPD so that it works by task, not in general.
Yes, Bill, I understand that, but there are uses for the cog besides running LMM kernels.
chip, I can't give you any real use examples right now, but I think it would be good if setquad could be called to move the quad mappings without clearing. So if it isn't difficult, I think clearing should be optional somehow. Is the NR/WR bit available?
I agree, Roy. Integrating clearing somehow into SETQUAD would be nice. We've got the Z and C bits which I can cause not to do anything. Biggest problem is what do you call it? Seven characters, max, or you blow the tab stop. SETQUAD vs SETQUAZ or ZETQUAD?
I agree, Roy. Integrating clearing somehow into SETQUAD would be nice. We've got the Z and C bits which I can cause not to do anything. Biggest problem is what do you call it? Seven characters, max, or you blow the tab stop. SETQUAD vs SETQUAZ or ZETQUAD?
This might sound dumb but can't we say SETQUAD for setting without clearing and the current SETQUAD would then be CLRQUAD?
I agree, Roy. Integrating clearing somehow into SETQUAD would be nice. We've got the Z and C bits which I can cause not to do anything. Biggest problem is what do you call it? Seven characters, max, or you blow the tab stop. SETQUAD vs SETQUAZ or ZETQUAD?
I agree, Roy. Integrating clearing somehow into SETQUAD would be nice. We've got the Z and C bits which I can cause not to do anything. Biggest problem is what do you call it? Seven characters, max, or you blow the tab stop. SETQUAD vs SETQUAZ or ZETQUAD?
I'll make a DE2_115 and StratixIII version a little later. I want to address the QUAD clearing issue and get REPS/REPD so that it works by task, not in general.
Comments
For Assembly programmers Little.
For people that write GCC --- Can give big problems
This would be more flexible, you can for example do something like that:
lmm rdquad pc ins1 nop ins2 nop jmpd #lmm ins3 nop ins4 nop add pc,#16AndyYes, that's what I was wondering about. Let me see...
I think this may work better:
lmm rdquad pc ins1 nop ins2 nop ins3 nop jmpd #lmm ins4 nop add pc,#16I don't mind such flexibility, as long as it does not slow things down...
i was posting a way i thought you could separate the first serquad & readquad from the subsequent readquad loop so that each part could be verified.
However i seechip has found a bug. Great work guys. much better to find this now. makes us happy chip released the emulation code.
i am expecting to join you with the fun around xmas although sneaking away from the family might not go down so well.
It looks like it would be kind of messy at this point. I think I'll just make it so that there's one address that doesn't need to be quad-aligned.
I figured you could do what you were attempting above like this:
ins0 nop ins1 nop ins2 nop ins3 nop jmpd #ins0 add pc,#16 nop rdquad pci will be using readquads for fast loading of binary overlays.
In my opinion ---> Most usable
Could SETQUAD zero the cache registers? That way they would be guaranteed to execute as NOP's first pass through the loop.
In the code below, would the rdquad ever execute? I thought JMPD only had two delay slots - or is my memory playing tricks on me?
I also have no problem if the one cog address must be quad aligned. This is really a minor problem compared with the LMM code in hub ram, that must be structured in quad packets. I already can see a lot of nops in a GCC generated code.
Andy
All delayed jumps have 3 delay slots - See also Chips post #50 in this thread.
There are three instruction slots that must be filled in a single-task JMPD scenario.
I've been thinking about some way to clear the QUADs, as it would make things tidy. On cog startup, they contain the data loaded into $1F4..$1F7.
Does anyone have any thoughts about SETQUAD clearing the registers? I have it set up now so that if you do a SETQUAD $1F8..$1FF the QUADs go into hiding. The hiding case might be a convenient time to clear the QUADs. Does anything think you might want to do a SETQUAD to simply move them, without clearing them?
The reason I'd like the quad cache cleared at a SETQUAD is so that a tight RDQUAD LMM loop will not execute random code.
Andy:
Thanks! Jeez my memory is going... or is that lack of sleep... or lack of cofee...
Chip:
Thanks, I don't know why I had a memory error on that. I'd better check my ECC bits.
How about SETQUAD D wz means clear the cache, without wz does not clear it?
The reason I'd like it cleared is the problem you pointed out many messages ago - the LMM look running random instructions on the first pass through the loop.
I think that answer Yours last question.
Hide ---> and clear --> BUT if moved to other position in COG -- leave as it is.
Frankly, I am still trying to figure out a case where it is useful to SETQUAD and NOT clear the cache... I am tring to find a use for that.
I think the Prop2PreliminaryFeatureList - PDF speaks of 2 delay slots, so there's a big chance that your memory still is okay.
Andy
Prop2_DEO_Nano_v2.zip
I'll make a DE2_115 and StratixIII version a little later. I want to address the QUAD clearing issue and get REPS/REPD so that it works by task, not in general.
Best case as I see it was Yours proposal.
give all possibility's.
My one as second one if other things not work.
chip, I can't give you any real use examples right now, but I think it would be good if setquad could be called to move the quad mappings without clearing. So if it isn't difficult, I think clearing should be optional somehow. Is the NR/WR bit available?
Thanks.
Good if REPx can work with task's --- Give more flexibility
Wifey is going to kill me... more Prop2 play time :-) :-) :-)
REPS/REPD working by task would be great.
I agree, Roy. Integrating clearing somehow into SETQUAD would be nice. We've got the Z and C bits which I can cause not to do anything. Biggest problem is what do you call it? Seven characters, max, or you blow the tab stop. SETQUAD vs SETQUAZ or ZETQUAD?
Why not simple.
SETQUAD D, wz
SETQUAD #n, wz
Ps. else new directive
rz
Does not clear:
SETQUAD D
SETQUAD #n
Does clear:
SETQUAD D, wz
SETQUAD #n, wz
or
SETQUADZ D, wz
SETQUADZ #n, wz
QM for Quad Mapping
I just tried to re-program my Nano, and I got:
"Error: File Z:/2012/prop2/Prop2_DEO_Nano_v2/DE0_Nano_Prop2.jic is corrupted"
I donloaded the zip twice, an tried it about four times.
Help!
I think it will be more flexible if it can be organized in same MNEMONIC with adding only extra directive
wz --- Else if Chip make new one ---- Flush
I don't had any problems with reprograming