Why get the P2 Emulator?
T Chap
Posts: 4,223
For most of you guys this is obvious. I am assuming that the main reasons would be:
1. Get a jump start on testing the new code and features.
2. Start porting P1 code to the P2.
Is there anything else? I am considering getting the 6 core version to get started for the reasons above, but wanted to see what other benefits there were to going through the learning curve to get it up and running.
1. Get a jump start on testing the new code and features.
2. Start porting P1 code to the P2.
Is there anything else? I am considering getting the 6 core version to get started for the reasons above, but wanted to see what other benefits there were to going through the learning curve to get it up and running.
Comments
Would you like to learn about the P2 in an interactive mode. For now, only Forth will do it. And both Tachyon Forth and PropForth seem to have plans to support the P2 with lots more i/o pins and ADC directly available at the pins.
I guess CatalinaC and GCC might want an early headstart as well.
And then, there is the huge step up in video ability.
Myself, I am a lowly noob - I will just wait for the P2 and get the real thing ASAP. But it would be nice to not have to wait to load the software and applications that I am hoping for.
As for the Forth solution, I think Peter is close to having Tachyon running on the P2. He may already be up and running and just having too much fun to let us know.
I think what Chip and Parallax did by releasing the emulator to anyone who wants to buy the FPGA is fantastic and just another one of the reasons I like Parallax so much!
I thought the same thing until I realized the board can do so much more than just run an emulator. Get a DE0 and explore the universe of FPGA's t'boot! It's a magical land!
For $110.00 including shipping I could not turn down this opportunity either as part of my continuing education having 0 FPGA experience.
Also gives me another reason to buy the new adapter board from parallax that Sapieha has designed to support the DEO. Really nice to see parallax keeping the "ring 0" crowd excited with the release of the emulator images and Chip's helpful comments while they all wait for the first shuttle results. And finally I want to run Peter's Tachyon P2 FORTH on the P2 emulator, there I said it.
As for me, I'm waiting for the actual chip.
One is I really enjoy learning Propeller related things. Emulation is perfect to continue doing that.
The other is FPGA learning. This is a great motivator. Get familiar with the tech with it acting as a P2, then go for combination projects once we get real P2 chips.
Oh, and the word "sardware" comes to mind...
I must be strong...I must be strong....
IMHO, if you can swing it, having multiple COGS is likely a great experience, though I suspect we are soon to be very impressed with what can be done on one COG!
Most powerful are have one of both ----> That give even possibility to test-writ drivers for communication betwen 2 Propellers II
Unless I have badly misunderstood the conversation... the PropII will make this sort of thing rather unnecessary. I personally don't have the time... just lots of desire. In looking at the natural progression of Prop I development, it is easy to see the PropII doing all of this
and more. Is there a market? Lattice thinks so:) A stereo camera I can control with a Prop II... Lordy, Lordy.
Rich
I was thinking the same thing. What's that saying?
I think that's the way it goes.
Huh? (I hear a ghostly voice.) What's that you say? "Gratification delaaaayed is gratification deniiiied." Stop that! Be still! Patience is a virtue!
-Phil
For me --- Today is already to late
Looks like I have to patiently wait until the most final product comes out from the factory.
Could we get engineering samples for the first batch if it is released? I can't wait to play with Prop2's multiply/divide stuff and the DAC inside.
There is, however, research on making a hybrid processor with a "soft peripheral" of an FPGA core and a compiler that analyzes the code, and for the heavily used or slow portions will automatically "compile" a peripheral on the FPGA that makes your code run faster. That's something to watch out for, along with a more intuitive FPGA programming paradigm than VHDL or Verilog.
Ha, try telling that to the guys who do high frequency stock market trading with FPGA's
http://www.hftreview.com/pg/blog/mike/read/55950
Back in 2007, I worked on a vector motor drive implementation on FPGA. I used Tensilica Xtensa tools to do just what you described.
In Altera Quartus You not need work VHDL or Verilog.
You can made al Yours work as SCH's -- That quartus compile that to FPGA configuration file.
That said, there are now a bunch of soft processors ARM's, Coldfire, PPC's, all with GNU C compiler tool chains. The same thing for NIOS and Blaze soft cores.
Xynq goes all the way by being a programmable system on a chip.
FPGA's are also good for emulating retro systems like the Amiga or Atari ST or extending them. Take a DE1 and turn it into a Amiga. I know it's weird but there is a segment out there that does it.
I guess the most compelling argument has to be "because the PII in emulation is here, right now." The final PropII is still in development. Everyone believes that release is right around the corner... but: Parallax has never done some of what it is trying to do. And until they have done it... there is always the possibility that some of the information that they are relying upon is either incomplete or inaccurate. Incomplete is more likely, but I can never get "inaccurate" out of my skull. All it takes is one little problem and the whole program gets delayed. It has happened to just about everyone who has ever developed anything. This is a little company... with a very big job.
Take the PII in emulation and run with it as fast and as far as you can,
Rich
First of all can we not call it an "emulator"?. What is on offer is the actual VHDL/Verilog design of the chip. The same as will be used in the production PII. Give or take a few adjustments required for the hardware it is instantiated in.
Reasons:
1) You have a PI program you want to optimize or expand for PII. Nice to have a test bed for it prior to arrival of the real thing.
2) Perhaps the same for hardware designs.
3) You are building a language compiler or interpreter for the PII and would like to know it will work when the time comes.
4) Let's face it, there may still be bugs in the PII design. Better if as many people as possible exercise it prior to committing to silicon.
5) You just can wait for "Chipmas" so you have to have a toy now.
6) The desire to get into FPGA's seems a natural for anyone interested in computing and how to design a CPU or other logic.
7) A ton of other reasons...
No. It's the real thing, logic element for logic element, connection for connection. Yes I know it's implemented in an FPGA and not custom made silicon but so what?
"simulate" or "emulate" implies something trying to behave something else. But this is the thing itself (silicon aside).
Is an "emulation" of a mathematician any less a mathematician than a "real" mathematician?