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[C3Synapse] usability challenge — Parallax Forums

[C3Synapse] usability challenge

kuronekokuroneko Posts: 3,623
edited 2012-10-25 02:53 in Propeller 1
The Good
  • You get half a Meg of SRAM (primarily) for your C3.
The Bad
  • suffers from the Hydra effect, i.e. C3 VGA can't be used at the same time (minor issue)
  • SPIN driver: doesn't compile, block read and fill are broken (fix is available at Jeff's place)
  • PASM driver: block read/write and fill are broken, API makes alignment assumptions (but doesn't tell you)
  • public driver interface is needlessly complicated (dummy parameters to always present a fixed number of them)
  • reliability of the test program has to be questioned as it doesn't spot the broken drivers
What is wrong with this picture? Is basic functionality too much to ask for these days?

Comments

  • David BetzDavid Betz Posts: 14,516
    edited 2012-10-24 04:46
    kuroneko wrote: »
    The Good
    • You get half a Meg of SRAM (primarily) for your C3.
    The Bad
    • suffers from the Hydra effect, i.e. C3 VGA can't be used at the same time (minor issue)
    • SPIN driver: doesn't compile, block read and fill are broken (fix is available at Jeff's place)
    • PASM driver: block read/write and fill are broken, API makes alignment assumptions (but doesn't tell you)
    • public driver interface is needlessly complicated (dummy parameters to always present a fixed number of them)
    • reliability of the test program has to be questioned as it doesn't spot the broken drivers
    What is wrong with this picture? Is basic functionality too much to ask for these days?
    There is a Propeller GCC cache driver for the C3Synapse board that worked when I tried it on a prototype board a few months ago but I no longer have the prototype or a production board so I can't say for sure if it works on the boards being sold now. Anyway, if you're looking for an example of how to interface to the Synapse SRAM you could look at that code. I'll attach it to this message.
  • kuronekokuroneko Posts: 3,623
    edited 2012-10-24 06:52
    Thanks for that but I wrote my own driver already (VGA has rather high bandwidth requirements). My point was more along the lines that not all users can or want to write their own drivers.
  • David BetzDavid Betz Posts: 14,516
    edited 2012-10-24 07:40
    kuroneko wrote: »
    Thanks for that but I wrote my own driver already (VGA has rather high bandwidth requirements). My point was more along the lines that not all users can or want to write their own drivers.
    Any chance your driver has byte read/write functions that could be used with the PropGCC cache driver to speed it up? Did you use counters? I know you're known for very fast code and I'd love to improve the speed of our cache drivers using your code! This actually applies across the board for all of our drivers. If you have fast SPI flash or sram code that would be very helpful as well!
  • kuronekokuroneko Posts: 3,623
    edited 2012-10-24 18:23
    Disclaimer: This driver is not usable with an out-of-the-box C3Synapse. In order to retain VGA capability I rewired the SRAM control port as SPI device #6. That said, running it on an unmodified board doesn't do any harm either (provided SPI select #6 is unused).

    The driver exports 4 basic functions, byte r/w and block r/w. The latter come without alignment restrictions (1n) and are therefore not the fastest implementations (2.5MB/s raw). However, you also get 4 extra commands (for direct mailbox usage) which enable 4n and 8n transfers (5MB/s and 10MB/s raw). 8n transfers require an extra cog.
  • David BetzDavid Betz Posts: 14,516
    edited 2012-10-24 18:45
    kuroneko wrote: »
    Disclaimer: This driver is not usable with an out-of-the-box C3Synapse. In order to retain VGA capability I rewired the SRAM control port as SPI device #6. That said, running it on an unmodified board doesn't do any harm either (provided SPI select #6 is unused).

    The driver exports 4 basic functions, byte r/w and block r/w. The latter come without alignment restrictions (1n) and are therefore not the fastest implementations (2.5MB/s raw). However, you also get 4 extra commands (for direct mailbox usage) which enable 4n and 8n transfers (5MB/s and 10MB/s raw). 8n transfers require an extra cog.
    Sounds great! I'll try it if I ever get a Synapse board again.
  • msrobotsmsrobots Posts: 3,709
    edited 2012-10-25 02:53
    Kuroneko,

    clkfreq/8, "pulling a lonesock"

    yeah. very nice code.

    thanks to you for showing this. I love it.

    I am again stealing with my eyes... Isn't PASM beautiful, sometimes?

    Enjoy!

    Mike
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