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New XMOS sliceKIT! — Parallax Forums

New XMOS sliceKIT!

Comments

  • Heater.Heater. Posts: 21,230
    edited 2012-10-23 08:25
    Except I suspect it does not have 16 cores at all. Only two each of which can run eight hardware scheduled threads.
    Recently they have revamped their web site and marketing which also involved renaming "cores" to "tiles" and "threads" to "logical cores".
    All of which I think is a bit dishonest.
    However the whole slice kit idea seems quite attractive.
  • LeonLeon Posts: 7,620
    edited 2012-10-23 08:31
    I spent a few minutes trying to find which device it uses, without success.

    I think you pointed out that there isn't any difference between XMOS cores/tiles and Propeller cogs!

    I'll be ordering one of the starter kits at the end of the month.
  • BeanBean Posts: 8,129
    edited 2012-10-23 08:35
    I have to agree, stating that it has 16 "cores" is more than a BIT dishonest.

    It has 2 cores which can each have 8 threads.

    I guess my PC has dozens of "cores"...

    Bean
  • LeonLeon Posts: 7,620
    edited 2012-10-23 08:37
    I just saw on the XCore Exchange forum that it actually has an L2 chip, with two processors.
  • Heater.Heater. Posts: 21,230
    edited 2012-10-23 08:44
    Exactly. I have been very vocal on the xcore forum pointing out that this new naming scheme is double speak and dishonest and smacks of some marketdroid MBA's taking over. I really can't believe The likes of David May and Ali whats name would have thought of this cockup.
    And why on earth can't they state the chip used in the front page of the slice kit blurb with a link to its data sheet.
    This all disturbs be greatly because I think xores are good stuff and deserve better.
    P.S. Do they now have to move the forum from xcore.com to xtile.com? It's all gone nuts over there.
  • LeonLeon Posts: 7,620
    edited 2012-10-23 08:48
    Yes, the marketing people seem to have taken over.
  • Bill HenningBill Henning Posts: 6,445
    edited 2012-10-23 14:18
    I was quite interested when I got the announcement... until I went over to their site and noted that they have:

    1) renamed cores "tiles"

    2) renamed threads "cores"

    I wonder if they will re-write all the documentation, samples, code, etc.

    Not a nice move.
  • Heater.Heater. Posts: 21,230
    edited 2012-10-24 00:59
    On the plus side we see that the Prop II now has 16 or 32 cores (or is it even more ?) with the new hardware scheduler feature:)
  • mindrobotsmindrobots Posts: 6,506
    edited 2012-10-24 06:18
    Bill Henning wrote: »
    1) renamed cores "tiles"

    2) renamed threads "cores"

    A rose is a rose is a rose......unless you are in marketing! :lol:
  • LeonLeon Posts: 7,620
    edited 2012-10-24 07:09
    "What's in a name? That which we call a rose
    By any other name would smell as sweet."
  • kwinnkwinn Posts: 8,697
    edited 2012-10-24 09:56
    I have to agree with those who are calling this marketing ploy dishonest. I also find it a bit insulting that they consider us so stupid that we would swallow this kind of Smile.
    It's not even that I have a problem with hardware scheduled threads, done properly I think they are a great idea for splitting the cpu power between threads. I prefer to deal with companies that provide clear, honest, and straight forward information on their products, and feel that XMOS is doing themselves a great disservice by using this kind of marketing.
  • Heater.Heater. Posts: 21,230
    edited 2012-10-24 12:13
    kwinn,
    It's not even that I have a problem with hardware scheduled threads, done properly I think they are a great idea for splitting the cpu power between threads
    Thing is, in the XMOS architecture even if your cpu is clocked at 400MH, say, a single thread can only dispatch instructions at 100MHz. One quarter the clock speed. But it can also dispatch 2, 3, or 4 threads at 100MHz each. This is all to do with their instruction pipeline. So to get maximum performance you want to be running at least 4 threads. After 4 threads time gets divid up between threads and the exaecution speed of each drops accordingly.

    In addition from 1 to 4 threads are deterministic in timing. All instructions take the same time and starting and stopping threads will not vary the speed of the ones currently executing.

    So in a way an XMOS thread can be seen as a "logical core" provided you stick to only using 4 threads and that chip in the slice kit has 8 of them, 4 per "tile".

    Start using using more that 4 threads on a processor and the timing of the threads changes. At which point the "logical core" idea falls down.

    Leon,

    What's in a name? It's not really a case of a name. The words "core" and "thread" have meanings we are all used to. They are descriptive of the product on offer no matter what its name is. If the description is confusing or downright misleading it is wrong.
  • David BetzDavid Betz Posts: 14,519
    edited 2012-10-24 12:17
    Heater. wrote: »
    Thing is, in the XMOS architecture even if your cpu is clocked at 400MH, say, a single thread can only dispatch instructions at 100MHz. One quarter the clock speed. But it can also dispatch 2, 3, or 4 threads at 100MHz each. This is all to do with their instruction pipeline. So to get maximum performance you want to be running at least 4 threads. After 4 threads time gets divid up between threads and the exaecution speed of each drops accordingly.

    In addition from 1 to 4 threads are deterministic in timing. All instructions take the same time and starting and stopping threads will not vary the speed of the ones currently executing.

    So in a way an XMOS thread can be seen as a "logical core" provided you stick to only using 4 threads and that chip in the slice kit has 8 of them, 4 per "tile".
    Can't you also get 8 determinstic threads as long as you guarantee that all 8 threads are always running? They may just put unused threads in an idle loop rather than stopping them to give predictable (but slower) performance across all 8 threads.
  • localrogerlocalroger Posts: 3,452
    edited 2012-10-24 15:57
    I was equally ticked back in the day when IBM called the 8088 a 16-bit chip even though it had an 8-bit path to memory and, given its architecture, actually performed worse than even an 8-bit chip (much less a real 16-bit chip) at similar clock speeds.

    The marketing people tend to win.
  • kwinnkwinn Posts: 8,697
    edited 2012-10-24 16:35
    @localroger

    That was IBM. Intel provided all the information for the chip in it's data sheet so you knew up front that the internal architecture was 16 bit, while the access to memory was 8 bit. They were also candid about the system cost reasons for doing that.

    @Heater

    RE: 
    Thing is, in the XMOS architecture even if your cpu is clocked at 400MH, say, a single thread can only dispatch instructions at 100MHz. One quarter the clock speed. But it can also dispatch 2, 3, or 4 threads at 100MHz each. This is all to do with their instruction pipeline. So to get maximum performance you want to be running at least 4 threads. After 4 threads time gets divid up between threads and the execution speed of each drops accordingly.

    I thought it would be something like that although I have not researched it. Essentially multiple program counters in hardware accessing instructions round robin style like the cogs access hub ram. More efficient than software threading and still gives deterministic timing, at least for 4 threads. Might even be deterministic for more threads albeit at lower speeds.
  • Heater.Heater. Posts: 21,230
    edited 2012-10-24 16:48
    David Betz,
    Can't you also get 8 determinstic threads as long as you guarantee that all 8 threads are always running?

    Yes you can.

    Problem is that to be consistant requires effectively halving the speed of your device.

    Consider that on the Prop we can happily mix and match objects in our projects, perhaps all written by differnt people, pehaps pulled from OBEX or the forum perhaps supplied by the language system we are using. We can do this safe in the knowledge that none of those alien objects can upset the timing of our application.

    For this to be true in the XMOS world we have to:
    a) Ensure that all codes we use assume a max of four threads running or
    b) Ensure that all codes assume all threads are running all the time and accept half the performance or
    c) Use the XMOS timing analysis tools to check that no matter what we throw in there our timing requirements will be met.

    Item c) there is excellent by the way, my only beef with all this is that the timing analysis may well tell me that the mix of codes I have won't meet my deadlines and I have to pull someting out. This cannot happen on the Prop.

    And that is why renaming "threads" as "cores" is dumb and/or dishonest.
  • Heater.Heater. Posts: 21,230
    edited 2012-10-24 17:04
    kwinn,
    Essentially multiple program counters in hardware accessing instructions round robin style like the cogs access hub ram. More efficient than software threading and still gives deterministic timing, at least for 4 threads.
    That's exactly it.
    Might even be deterministic for more threads albeit at lower speeds.

    Yes threads slow down after the 4th one. Provided there is always a constant number of threads running they are deteministic.

    I should point out the with XMOS you are not expected to be writing in assembler and counting instructions in order to get your timing right.
    Rather you work in a high level language, XC, which is like C tweaked for parallelism. The dev tools include a timing analyser that can tell you how long code sequences take to run. You can set up timing requirements on critical codes and the compiler will warn you if hey are not met.

    Together with some funky hardware support for events like pin changes, timeouts, channel communications you can meet some amazingly tight time constraints.

    It's all very cool actually.

    Oh and note that the Prop II is now getting a very similar round robin hardware scheduled thread mechanism. Good times ahead.
  • David BetzDavid Betz Posts: 14,519
    edited 2012-10-24 19:12
    Heater. wrote: »
    David Betz,



    Yes you can.

    Problem is that to be consistant requires effectively halving the speed of your device.
    Yeah, that's what I figured. However, it might still be acceptable if you don't need the extra speed but do need determinism.
  • jazzedjazzed Posts: 11,803
    edited 2012-10-24 22:03
    localroger wrote: »
    ... The marketing people tend to win.
    They tend to get much bigger budgets too. :)
  • LeonLeon Posts: 7,620
    edited 2012-10-25 04:34
    Here is a nice XMOS design win:

    http://www.electronicsweekly.com/Articles/20/06/2012/53925/sennheiser-design-win-for-xmos.htm

    They seem to be cornering the market in high-end audio applications.
  • mindrobotsmindrobots Posts: 6,506
    edited 2012-10-25 06:46
    jazzed wrote: »
    They tend to get much bigger budgets too. :)

    And bigger bonuses too!

    After all, it is the oldest profession! :lol:
  • LeonLeon Posts: 7,620
    edited 2012-10-25 06:48
    Second oldest!
  • RDL2004RDL2004 Posts: 2,554
    edited 2012-10-25 06:55
    I think they are the same profession :)
  • jazzedjazzed Posts: 11,803
    edited 2012-10-25 13:52
    Leon wrote: »
    Second oldest!
    Where's your hat Leon?

    @Rick, seems like shipping and receiving is a closer analogy.
  • JordanCClarkJordanCClark Posts: 198
    edited 2012-10-26 02:52
    RDL2004 wrote: »
    I think they are the same profession :)
    You mean they're farmers? :confused:
  • LeonLeon Posts: 7,620
    edited 2012-10-29 08:49
    I ordered a sliceKIT yesterday from Digi-Key (they now have eight left), and have just had an email saying it has been shipped. I should get it in three days or so.
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