I agree, the idea is really cool but the product is not available. However, it takes only 8 Parallax Propeller chips and a lot of fun to make a machine with 64 cores and the chips are available for a list cost of $63.92. For example, the SuperTronic 8 machine is a project with with 64 Cog computers, made from eight Level II enhanced Propeller chips working in parallel. Blogs at: supertronic erasupertronic 12
Except bolting together a bunch of Propeller chips will not get you any performance gains, except in some simple cases. You need the shared memory with large memory bandwidth or you need other high speed core to core communications to realise the benefits.
The 16 core Epihany III looks like an interesting place to start with their technology and it's exciting that they are taking their expensive developer boards and trying to repackage them in a more affordable hobbyist/hacker price range.
I'm not committing to a pledge yet, but I'm going to keep an eye on them and do some more reading.
Interesting project, but a little skewed by the desire to raise money.
A large portion of what they plan, is already on a RaspPi, and the stuff that is special to them, is what they should focus on.
If I was doing this, I'd release in two steps :
Step one would be slave(s*) to RaspPi, that focuses on getting their silicon on as many desks as possible.
*If they have 4 chips on a board, also do a 1 chip board.
Step 2 would be to improve any bottlenecks with a RaspPi, with their own ARM PCB variant.
I see the Per-core speed DROPPED, and the per-core SRAM is locked to 32K in both devices.
So a VERY focused problem will be needed for these to really shine.
Few seem to be chasing an obvious market opening, which is a Graphics GPU, with VideoRAM included.
Closest is the stacked-die chips in RaspPi, and Nuvoton have TQFP128 dual die offerings.
A large portion of what they plan, is already on a RaspPi
I don't understand. Which part of the Raspi is anything to do with parallel processing?
Yes, the Raspi has a GPU with a lot of parallel CPU's inside dedicated to graphics processing but that is not really available for general use.
Yes they have an ARM chip on board to control the whole thing but then they have to. As far as I can tell all those cores are not up to running an OS to control everything.
I see the Per-core speed DROPPED, and the per-core SRAM is locked to 32K in both devices.
So a VERY focused problem will be needed for these to really shine.
I hate to say this but the Propeller and even Propeller 2 are limited to 2K bytes per core and we seem to think that's not that limiting. At least this board has an ARM to run the "main loop".
Yes, the Prop cores are limited to 2K bytes per core. But there are resons why we do not see that as limiting:
1) Every core can directly access all I/O pins. That is to say that every core can perform some real-world/real-time functionality independently of any other. Great for the "soft peripherals idea.
2) Every core has it's own counters and video hardware. Which again helps with the "soft peripheral" idea.
3) We are not expecting the Prop to be a high performance parallel computer in the general sense of turbo charging compute intensive algorithms.
Perhaps when we start talking about multi-core parallel processing we should be more clear about what we mean.
At least this board has an ARM to run the "main loop".
It crossed my mind a few times, and I might even have suggested sometime, that a Prop with an ARM core on one chip might be perfect for a lot of embedded systems. The ARM runs Linux an manages high level stuff, networking, USB etc, the Prop does the specialized bit twiddling and I/O.
Anyway just now I will be content to hook a Prop 1/2 to a Raspi to achieve that.
It crossed my mind a few times, and I might even have suggested sometime, that a Prop with an ARM core on one chip might be perfect for a lot of embedded systems. The ARM runs Linux an manages high level stuff, networking, USB etc, the Prop does the specialized bit twiddling and I/O.
Anyway just now I will be content to hook a Prop 1/2 to a Raspi to achieve that.
I think a number of people have tried to convince Chip of that but so far without any success. :-)
Edit: Another problem might be the cost of licensing an ARM core.
... I might even have suggested sometime, that a Prop with an ARM core on one chip might be perfect for a lot of embedded systems.
The problem with this, is what size arm and what about CODE memory ?
Suddenly you move from general, into specialised and the TAM shrinks.
Smarter to add silicon for fast DMA slaves, and even dual-port memory access models, so that almost ANY external host can communicate with a Prop. That amount of silicon is tiny.
Some Arms support QuadSPI in Silicon, so that is an established link system.
Marketroid talk again ... "OCTEON III also features a revolutionary, low latency coherency architecture that enables multiple OCTEON III chips to appear as a single logical high-performance processor with up to 384 cores, providing up to 960GHz compute, up to 800+ Gbps of application performance and up to 2 Terabytes of memory capacity."
"up to 384 cores" - Okay, that one is straight forward at least, if not a little misleading. It later says 48 cores per chip, which makes it up to 8 chips closely linked together.
"up to 960GHz compute" - Hmm, not my favourite compute measure! My best guess is they mean 960,000 MIPS (States integer core explicitly in the block diagram). So, 960000 / 384 = 2500 MIPS per core. And further on down the promo it says "cores up to 2.5GHz", so that makes it one instruction per clock.
"up to 800+ Gbps of application performance" - *application performance*?! How vague is that? Are they talking about Ethernet?, RAM?, interconnect?, or what?
"2 Terabytes of memory capacity" - It later says 4x 72bit DDR3-2133 per chip so it's fare honking along. Same story as the first point - divide by 8 for the per chip figure. Limited by caching range presumably? Hopefully not just by current sized RAMs at the time of publishing.
The problem with this, is what size arm and what about CODE memory ?
Suddenly you move from general, into specialised and the TAM shrinks.
Smarter to add silicon for fast DMA slaves, and even dual-port memory access models, so that almost ANY external host can communicate with a Prop. That amount of silicon is tiny.
Some Arms support QuadSPI in Silicon, so that is an established link system.
Actually, size of code memory brings up an interesting point. If Parallax were able to make a Propeller chip with an ARM core on it that ran code from flash, they would almost certainly also be able to make a COG-only chip with onboard flash. We've been told repeatedly that this isn't possible using the technology they use for the Propeller so that could be a reason they don't consider a more traditional core in addition to COGs as well.
Actually, size of code memory brings up an interesting point. If Parallax were able to make a Propeller chip with an ARM core on it that ran code from flash, they would almost certainly also be able to make a COG-only chip with onboard flash. We've been told repeatedly that this isn't possible using the technology they use for the Propeller so that could be a reason they don't consider a more traditional core in addition to COGs as well.
Yes, Flash is a more costly process, and it is slow. Even now, vendors crow about 100MHz Flash, even at FAB nodes well ahead of Prop 2 (read a lot more expensive)
Analog Devices pulled out of flash, and chose RAM based DSPs because of Speed issues, and the Prop 2 follows this route.
Besides, the ARM+FLASH is now a crowded, commodity market, which Parallax are best avoiding.
That's why I think it is smarter to allow easy connection to one of these commodity devices alongside a Prop.
Yes, Flash is a more costly process, and it is slow. Even now, vendors crow about 100MHz Flash, even at FAB nodes well ahead of Prop 2 (read a lot more expensive)
Analog Devices pulled out of flash, and chose RAM based DSPs because of Speed issues, and the Prop 2 follows this route.
Besides, the ARM+FLASH is now a crowded, commodity market, which Parallax are best avoiding.
That's why I think it is smarter to allow easy connection to one of these commodity devices alongside a Prop.
Sounds good to me. Who's going to make a board with an ARM and a Propeller 1/2? :-)
Actually, Andre' LaMothe already has a board with a 16 bit PIC and a Propeller called the Chameleon. The trouble is, the SPI connection between the chips is fairly slow. I think the Propeller 2 should allow faster CPU to CPU communications.
The problem IMO with LaMothe's Chameleon he coupled the Prop to under powered micros. He should have went with a ARM or a PIC32. Still there isn't anything stopping a person from buying a cheapo Olimex ARM or PIC32 board and interfacing it with a Prop board. Have the ARM run NetBSD or Linux while the Prop(s) does all the real-world I/O. I think of It as a best of breed solution.
I think I may back this project. If it reaches its goal, this would be an interesting unit. But its unlikely to reach $750k in 30 days, so no actual cost.
Win either way.
A large portion of what they plan, is already on a RaspPi, .....
....Step one would be slave(s*) to RaspPi, that focuses on getting their silicon on as many desks as possible.
Step 2 would be to improve any bottlenecks with a RaspPi, ...
I may have mentioned this before, but we've got the synchronous serial channels thing going with Propforth and Go Language running on the rapsberry pi. There's only one physical connection between the linux node and the prop node(s) but that are 8 channels (by default). If the application needs a whole load of I/O pins and dedicated processors, one can add as many prop chips as needed. The RPI is fast enough to keep up with all the channels, and propforth is set up to handle distributing the data streams at maximum rate. Might be the best of both worlds. Not the solution for every application, but might be handy for deterministic execution and lots of I/O streams. And affordably cheap.
C.W. (ctwardell) wrote: Please explain these "Level II enhanced Propeller chips" and where they can be purchased.
Mindrobots wrote: Yessss! We wants them, we wants them for my Precious!
I work making humanoid brains. This led to simple Level I enhancements inside the chip (more processors, speed, function). A plateau was surpassed, resulting in Level II. A Supertronic Level II brain will be offered when ready. Updates will appear here first: http://humanoidolabs.blogspot.tw/
Interesting devices but clearly not comparable to Propellers. Those cores do not have direct access to I/O pins. Those chips are not designed for the real-time, embedded, "software as hardware" space that the Prop is designed for. They look like they are designed more for turbo charging compute intensive applications.
C.W. (ctwardell) wrote: Please explain these "Level II enhanced Propeller chips" and where they can be purchased.
Mindrobots wrote: Yessss! We wants them, we wants them for my Precious!
I work making humanoid brains. This led to simple Level I enhancements inside the chip (more processors, speed, function). A plateau was surpassed, resulting in Level II. A Supertronic Level II brain will be offered when ready. Updates will appear here first: http://humanoidolabs.blogspot.tw/
So you they don't really exist?
So saying "I agree, the idea is really cool but the product is not available." could just as easily apply to the Level II enhanced Propeller chips and the Supertronic Level II brain...
C.W. a product could be slated for future release, with a first announcement here. The blog shows a functional supertronic prototype on a solderless breadboard being tested with 12 L2 chips.
jdolecki
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Please explain these "Level II enhanced Propeller chips" and where they can be purchased.
C.W.
Yessss! We wants them, we wants them for my Precious!
Hmm... I think we had this dicussion before...
The 16 core Epihany III looks like an interesting place to start with their technology and it's exciting that they are taking their expensive developer boards and trying to repackage them in a more affordable hobbyist/hacker price range.
I'm not committing to a pledge yet, but I'm going to keep an eye on them and do some more reading.
http://www.mips.com/Prodigy/MIPSProdigyPreviewPresentation3_27_11F.pdf
48 cores per package shipping now: http://cavium.com/OCTEON-III_CN7XXX.html
Cavium has a good history starting with the 16 core package - I worked with it 8 years ago.
Interesting project, but a little skewed by the desire to raise money.
A large portion of what they plan, is already on a RaspPi, and the stuff that is special to them, is what they should focus on.
If I was doing this, I'd release in two steps :
Step one would be slave(s*) to RaspPi, that focuses on getting their silicon on as many desks as possible.
*If they have 4 chips on a board, also do a 1 chip board.
Step 2 would be to improve any bottlenecks with a RaspPi, with their own ARM PCB variant.
They seem to have development kits, but no price mentioned on Kits or chips :
http://www.adapteva.com/products/eval-kits/emek4/
http://www.adapteva.com/products/eval-kits/emek3/
I see the Per-core speed DROPPED, and the per-core SRAM is locked to 32K in both devices.
So a VERY focused problem will be needed for these to really shine.
Few seem to be chasing an obvious market opening, which is a Graphics GPU, with VideoRAM included.
Closest is the stacked-die chips in RaspPi, and Nuvoton have TQFP128 dual die offerings.
I don't understand. Which part of the Raspi is anything to do with parallel processing?
Yes, the Raspi has a GPU with a lot of parallel CPU's inside dedicated to graphics processing but that is not really available for general use.
Yes they have an ARM chip on board to control the whole thing but then they have to. As far as I can tell all those cores are not up to running an OS to control everything.
Yes, the Prop cores are limited to 2K bytes per core. But there are resons why we do not see that as limiting:
1) Every core can directly access all I/O pins. That is to say that every core can perform some real-world/real-time functionality independently of any other. Great for the "soft peripherals idea.
2) Every core has it's own counters and video hardware. Which again helps with the "soft peripheral" idea.
3) We are not expecting the Prop to be a high performance parallel computer in the general sense of turbo charging compute intensive algorithms.
Perhaps when we start talking about multi-core parallel processing we should be more clear about what we mean.
It crossed my mind a few times, and I might even have suggested sometime, that a Prop with an ARM core on one chip might be perfect for a lot of embedded systems. The ARM runs Linux an manages high level stuff, networking, USB etc, the Prop does the specialized bit twiddling and I/O.
Anyway just now I will be content to hook a Prop 1/2 to a Raspi to achieve that.
Edit: Another problem might be the cost of licensing an ARM core.
The problem with this, is what size arm and what about CODE memory ?
Suddenly you move from general, into specialised and the TAM shrinks.
Smarter to add silicon for fast DMA slaves, and even dual-port memory access models, so that almost ANY external host can communicate with a Prop. That amount of silicon is tiny.
Some Arms support QuadSPI in Silicon, so that is an established link system.
Marketroid talk again ... "OCTEON III also features a revolutionary, low latency coherency architecture that enables multiple OCTEON III chips to appear as a single logical high-performance processor with up to 384 cores, providing up to 960GHz compute, up to 800+ Gbps of application performance and up to 2 Terabytes of memory capacity."
"up to 384 cores" - Okay, that one is straight forward at least, if not a little misleading. It later says 48 cores per chip, which makes it up to 8 chips closely linked together.
"up to 960GHz compute" - Hmm, not my favourite compute measure! My best guess is they mean 960,000 MIPS (States integer core explicitly in the block diagram). So, 960000 / 384 = 2500 MIPS per core. And further on down the promo it says "cores up to 2.5GHz", so that makes it one instruction per clock.
"up to 800+ Gbps of application performance" - *application performance*?! How vague is that? Are they talking about Ethernet?, RAM?, interconnect?, or what?
"2 Terabytes of memory capacity" - It later says 4x 72bit DDR3-2133 per chip so it's fare honking along. Same story as the first point - divide by 8 for the per chip figure. Limited by caching range presumably? Hopefully not just by current sized RAMs at the time of publishing.
That's a lot of pins btw!
Yes, Flash is a more costly process, and it is slow. Even now, vendors crow about 100MHz Flash, even at FAB nodes well ahead of Prop 2 (read a lot more expensive)
Analog Devices pulled out of flash, and chose RAM based DSPs because of Speed issues, and the Prop 2 follows this route.
Besides, the ARM+FLASH is now a crowded, commodity market, which Parallax are best avoiding.
That's why I think it is smarter to allow easy connection to one of these commodity devices alongside a Prop.
Actually, Andre' LaMothe already has a board with a 16 bit PIC and a Propeller called the Chameleon. The trouble is, the SPI connection between the chips is fairly slow. I think the Propeller 2 should allow faster CPU to CPU communications.
I notice no prices listed. Usually, if they don't show the price, nobody can afford it. Meaning a nobody like me.
I think I may back this project. If it reaches its goal, this would be an interesting unit. But its unlikely to reach $750k in 30 days, so no actual cost.
Win either way.
I may have mentioned this before, but we've got the synchronous serial channels thing going with Propforth and Go Language running on the rapsberry pi. There's only one physical connection between the linux node and the prop node(s) but that are 8 channels (by default). If the application needs a whole load of I/O pins and dedicated processors, one can add as many prop chips as needed. The RPI is fast enough to keep up with all the channels, and propforth is set up to handle distributing the data streams at maximum rate. Might be the best of both worlds. Not the solution for every application, but might be handy for deterministic execution and lots of I/O streams. And affordably cheap.
Mindrobots wrote: Yessss! We wants them, we wants them for my Precious!
I work making humanoid brains. This led to simple Level I enhancements inside the chip (more processors, speed, function). A plateau was surpassed, resulting in Level II. A Supertronic Level II brain will be offered when ready. Updates will appear here first: http://humanoidolabs.blogspot.tw/
So you they don't really exist?
So saying "I agree, the idea is really cool but the product is not available." could just as easily apply to the Level II enhanced Propeller chips and the Supertronic Level II brain...
C.W.