How many logic cells need a Propeller 1 to implement in FPGA?
pik33
Posts: 2,396
Or.. how many Propellers can be implemented in today produced FPGAs with ~100000 logic cells?
I am learning FPGAs now (at novice level/led blinking) and that is why this question raised in my head...
I am learning FPGAs now (at novice level/led blinking) and that is why this question raised in my head...
Comments
I've not seen numbers for Prop1, but there are many cores here
http://opencores.org/projects
and more FPGA numbers on controllers here
http://www.latticesemi.com/products/intellectualproperty/ipcores/mico32/index.cfm
http://www.latticesemi.com/products/intellectualproperty/ipcores/mico8/index.cfm
An exact clone of a Prop would be a little wasteful in a FPGA, but the time-slice approach Chip mentioned for Prop 2, could be nice to add to a Prop 1 / FPGA.
Using a FPGA just to replace a Prop 1 is unlikely to make economic sense, but if you already needed a largish FPGA, then a couple of COGs might come almost for free ?
eg a device like LCMXO2-7000HC-4TG144C is $11.55/100+ would have the RAM & Logic to do ?? COGs
-dan
So what's the problem? You are learning about FPGA's. All you ave to do is implement a Propeller chip in Verilog or VHDL from the published specifications and see if it fits in your device of choice or many such devices. Then you can tell us.
(I mean, someone other than Chip!)
Yes, I know there are ready made cores for FPGAs like NIOS. A simplest NIOS needs something about 6000 cells....
What I need is a network of simple logic units to build a neural network from it - for my study . An array of (how many I don't know at this time) Propellers can do it, to, but FPGA looks like better way to do this, so I started to learn these beasts. These logic units I need are much more simpler than Propeller's cogs, but I need some thousands of them. And then I need a "one core to rule them all"...
IIRC, the Prop1 was created using schematics, not a HDL. The Prop2 was delayed for some time (a year?) while Chip converted all his code to HDL.
"...one core to rule them all"
As you may know already, my favorite is the Zylin CPU core, ZPU. It's the smallest 32 bit processor design for FPGA. Desiged for minimal logic size rather than raw speed.There are VHDL and Verilog. implementations of it. It might be an excellent management core for your network where the heavy lifting is done by the neural net. There is a GCC compiler for it so writing you application code is easy.
http://opensource.zylin.com/zpu.htm
To make life easy there is the zpuino, project. http://http://papilio.cc/index.php?n=Papilio.ZPUinoIntroduction
http://forums.parallax.com/showthread.php?112850-Propeller-Simulation-in-Verilog
http://www.altera.com/education/univ/materials/boards/de0-nano/unv-de0-nano-board.html
and that links to another effort, which does have a build report
http://forums.parallax.com/showthread.php?107829-FPGA-based-soft-CPU-%28distant-relative-of-COG%29&p=763090&viewfull=1#post763090
http://forums.parallax.com/attachment.php?attachmentid=56673&d=1226208985
Seems 1204 Logic Elements, Cyclone II, partial single COG design (?), no MHz mentioned.