Spi sync
Ray0665
Posts: 231
How do two devices achieve initial reliable sync when communicating via SPI. I have a working prototype software module to allow SPI comm between the raspberry pi (master) and a propeller (slave) it works extremely well once sync is achieved, as long as I start the slave first so it is sitting there waiting for the comm to start, but if i reverse that and start the Pi first or just randomly stop and start sync up is not assured. I'm guessing that if the break occurs while the slave is transmitting it sits waiting for clocks that never arrive and when they do it is then transmitting while the master is and confusion is the rule till a proper reset.
I intend to post the software here once I get over this hurdle.
I intend to post the software here once I get over this hurdle.
Comments
Usually SPI uses the /CS line, as a RESET on the slave, so that should always sync on a new packet, after /CS goes active.
If you want to also cover packet fragments, and even clock glitches, one simple scheme is to count clock edges, and reject any frame of unexpected size.
As currently implemented the master controls both CS and Clk. The master begins transmitting a variable length packet the slave begins receiving a packet. Each transmission proceeds as follows cs low < N data bytes> cs high.
As I have it implemented the master sends a packet the slave receives a packet then the slave sends a packet and the master receives a packet and so on.
Later I expect to implement a command interpreter in the slave (but for now they take turns) which may help this since the slave will always receive unless told to transmit.
An added MOD 8 check on number of clocks, would give another safety net, but this mode needs SW to wait for CS high, before it decides to act on the packet.
so here is a zip of the current Raspberry PI <--> Propeller SPI comm software.